AM625: spi flash clok

Hi,

Which SDK are you using? Is it MCU PLUS SDK or Linux SDK?

Please check the flash datasheet, it will be mentioned there about the max frequency it can support.

Meanwhile please have a look at the supported clocking modes here:

Thanks,

Vaibhav

Hi Vaibhav

The sdk version is 10.01.10.04

The max freq we test is 166M.I think is phy mode.

We don't want it run 166M.The flash can't support 166M, it can only support about 100M.

How we can modify code to change the max freq as about 100M.

Hi Tom,

tom zhang said:

How we can modify code to change the max freq as about 100M.

If this were MCU+ SDK, then one way to change this would have been the SysConfig tool, where you would be able to just update the frequency.

Based on the SDK version you mentioned, you are using Processor SDK Linux for AM62x. I believe to change the frequency would require top level changes to the device tree source files.

Please have a read through the following: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/11_01_05_03/exports/docs/linux/Foundational_Components/U-Boot/UG-QSPI.html

Let me know if the section "spi-max-frequency:" helps you out.

Thanks,

Vaibhav

Hi Vaibhav:

The spi-max-frequency in dts as we set is not 166MHz, it is 25M, but the flash can work as 166M

Hi Tom,

tom zhang said:

The spi-max-frequency in dts as we set is not 166MHz, it is 25M, but the flash can work as 166M

Allow sometime for another expert to comment on this.

Thanks,

Vaibhav

Hi Tom, please take a look at cadence OSPI linux kernel driver drivers/spi/cadence_qspi.c (https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/spi/spi-cadence-quadspi.c?h=ti-rt-linux-6.12.y-arm32-cicd). Especially below functions:

• cqspi_config_baudrate_div

From what I see in documentation (below text extracted), DTS provides initial OSPI configuration but is not strictly enforced by the driver during runtime when PHY is enable. So, this probably this would need to be handle with a patch in the driver

3.1.1.6. OSPI/QSPI NOR/NAND — Processor SDK AM62x Documentation

Flash properties:

1. compatible: specifies the compatible string for the device, the operating system uses this string to identify and the match the driver for the device. Use ‘jedec,spi-nor’ for OSPI/QSPI NOR flashes and ‘spi-nand’ for OSPI/QSPI NAND flashes.

2. spi-tx-bus-width and spi-rx-bus-width: specifies the bus width in bits for SPI transactions when transmitting (tx) and receiving (rx) data. Set for ‘8’ for OSPI flashes and ‘4’ for QSPI flashes.

3. spi-max-frequency: defines the maximum frequency in Hertz at which the SPI bus can operate. Set 1/4th or 1/8th of ‘assigned-clocks’ value of ‘ospi0’ node for SDR and DDR mode respectively. If PHY Calibration is enabled, this value is ignored, and the maximum frequency is determined by the value specified in the ‘assigned-clocks’ property of ‘ospi0’ node.

4. cdns,read-delay: specifies the delay in clock cycles between the fetch of a command and responding to that command by the flash devices. This differs with flashes, try with different read delays starting from 0 and find the minimum read-delay at which the flash driver probes correctly.

thank you,

Paula

Hi Paula:

We enable PHY calibration, I tried to set the assigned-clock-rates of OSPI from 166666666 to 100000000,

But when boot up, board reads data error from flash.

As you say, the max freq is defined by assigned-clocks , the value in SDK is 

assigned-clocks = <&k3_clks 75 7>

How to change it ?

Hi Tom, yes clock ID 75 seems to be the correct one according with documentation (AM62X Clock Identifiers — TISCI User Guide). I found below E2E in which user changed PRUSS core clock. Please take a look and let me know if you can do something similar using "assigned-clock-rates"

AM625: Help setting PRUSS clock to 333MHz on AM6254 - Processors forum - Processors - TI E2E support forums

By the way which errors you got when booting up?

thank you,

Paula

I only changed the assigned-clock-rates as 100000000,the error is the data read from flash is error, my board can't boot up.

I don't how if I need to change other value of assigned-clocks or assigned-clock-parents

Tom, to understand better. If you use OSPI clock to 166MHz, without PHY (PHY disable) is your board booting? I want to see if there is any scenario where your board have been booting OK even if it is not to at most optimal speed, to rule out any other possible issue

Thank you,

Paula

你好，Paula：

How to disable PHY?Why should I disable it to boot up?

Hi Paula:

Coule you please reply to me?

My apology for my late reply. 

I see "phy-mode"  in "dts\upstream\src\arm64\ti\k3-am625-sk.dts". https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts?h=ti-linux-6.12.y#n730 I will double check this is the right place and come back to you, if it is you just need to delete it from there.

On the other hand, let me circle back some questions:

- In your original post you mentioned :"when I test, the max freq can be 166M" so, does this means you were able to boot before?

- If that is the case, how did you boot? using SD card?  

- If you can indeed boot, could you try "k3conf dump clock 75" and let us know the results? I want to see if you are able to see your SPI bus clock at 100MHz or if you still see 166MHz 

Thanks for your help,

Paula

Hi Paula:

- In your original post you mentioned :"when I test, the max freq can be 166M" so, does this means you were able to boot before?

Yes: my board can boot up normal.

- If that is the case, how did you boot? using SD card?  

SPI-nand

- If you can indeed boot, could you try "k3conf dump clock 75" and let us know the results? I want to see if you are able to see your SPI bus clock at 100MHz or if you still see 166MHz 

I don't understand "k3conf dump clock 75".

The SPI bus clock at 166Mhz only when flash do read,write,erase

Hi Paula:

I remove the phy-mode in ospi nodes in dts and change the assigned-clock-rates as 100M 

The image can boot up and the clock of flash reads writes erase up to 100M not 166M.

We don't support this cmd k3conf dump clock 75 in rootfs.

The spi nand is QSPI

Hi Tom, to confirm, now your system is booting up and you can see flash clock as 100M (instead of 166M)?

If so, great, but I would have a follow up question(s) for you.. If no, then please clarify me current status.

thank you,

Paula

Hi Paula:

Yes， it can boot up and the max flash clock is 100M

Hi Tom, thanks for your confirmation. 

After disabling PHY, which "assigned-clock-rates" did you end up using?

Paula

Hi Paula:

In dts, I set it as 100M

Hi Paula:

Can I remove the phy-mode in dts and set assigned-clock-rates as 100M?

Is there any problems when we use flash?

And the dts we use is k3-am62-main.dtsi and k3-am62-lp-sk.dts, not k3-am625-sk.dts.

Hi Tom, as mentioned below, Without PHY calibration you will use a divider to your clock. So, your OSPI Clock frequency will end up being 1/4 or 1/8 of 100MHz. There is no problem with disabling PHY except for performance, but this could be OK depending on the use-case and application.

Paula Carrillo said:

spi-max-frequency: defines the maximum frequency in Hertz at which the SPI bus can operate. Set 1/4th or 1/8th of ‘assigned-clocks’ value of ‘ospi0’ node for SDR and DDR mode respectively. If PHY Calibration is enabled, this value is ignored, and the maximum frequency is determined by the value specified in the ‘assigned-clocks’ property of ‘ospi0’ node.

Thank you,

Paula