SK-AM62B-P1: Impedance Calculation for High-Speed Traces on SK-AM62B-P1

Part Number: SK-AM62B-P1

Tool/software:

Dear TI Experts,

I am designing a custom SBC using the AM6254 Sitara SoC, following the SK-AM62B-P1 reference design. To ensure proper signal integrity, I need clarity on the impedance design targets used in the SK-AM62B-P1 board.

My confusion: calculations for asymmetric stripline, microstrip using IPC formulas differ from values implied in the SK-AM62B-P1 design.

Could you please provide details on(SK-AM62B-P1):

  • Layer-wise target impedance values (single-ended and differential microstrip/stripline) used for high-speed interfaces such as DDR4, SDIO, USB, Ethernet, HDMI, MIPI CSI/DSI, and LVDS.

  • The calculation methodology and simulation approach followed for impedance control in this design.

  • Formula or tools used for obtaining impedance value.

This information will help me properly align my stack-up and routing with the reference design.

Thanks & Regards,
Arijit