SK-AM62P-LP: DPI OUTPUT BT656

Wangpq

Prodigy 221 points

Part Number: SK-AM62P-LP
Other Parts Discussed in Thread: AM62P

Tool/software:

Hi:

DPI BT656 Display Useing Progressive mode On Dothinkey is OK.

But Project need BT656 Interlaced mode , and do signal format conversion to CVBS, output CVBS Display on IVI.

The pannel parame is ：

So How to Enable BT656 Interlaced mode, pls help!!!

22 days ago

0 Divyansh Mittal 22 days ago

TI__Expert 8710 points

Hi,
Please check the link provided in the second post of [FAQ] AM62P: Enabling BT.656 mode in DSS . There are some patches at the end of that thread.

0 Wangpq 18 days ago in reply to Divyansh Mittal

Prodigy 221 points

Hi，

Two displays（DSI + DPI） are used in the project，

The DSI interface display was originally fine, but now with the addition of DPI-BT656 and interlaced display patch, there is no signal at the DSI interface.

0 Divyansh Mittal 16 days ago in reply to Wangpq

TI__Expert 8710 points

I'll look into the patch on what could be causing this, though are you able to operate interlaced mode in DPI?

0 Wangpq 16 days ago in reply to Divyansh Mittal

Prodigy 221 points

Hi,

I test, merge DPI-BT656 patch case DSI no signal. No association with the DPI interlaced mode patch.

0 Tao Han 16 days ago in reply to Divyansh Mittal

TI__Expert 6465 points

Hi Divyansh:

We discuss with customer below is the pipeline about their display request:

Memory -> DSS0 -> Overlay 2 ->VP1 -> DPI -> BT.656 interleave output

Memory-> DSS1 -> Overlay 2 -> VP1 -> DSI

We think maybe the DPI-BT.656 patch affect all DSS0/DSS1 pipeline. But customer user case is 2 different display resolution and display mode.

Maybe those DPI patch use affect DSS0 and DSS1 keep the default configure method can resolve customer problem.

Could you please suggest just enable DPI-BT.656 interleave method at DSS0 modify method? We can try it.

Best Regards!

Han Tao

0 Divyansh Mittal 16 days ago in reply to Tao Han

TI__Expert 8710 points

Hi wangpq,
As I understand, your issue is currently not with the interlaced BT656 patch, but the initial progressive BT656 patch. Is this understanding correct?

Can you share the output of following:

dmesg | grep -e dsi -e dss
kmsprint --device=/dev/dri/by-path/platform-30200000.dss-card
kmsprint --device=/dev/dri/by-path/platform-30220000.dss-card

Please also share dts files and DSI overlays you have applied.

0 Divyansh Mittal 15 days ago in reply to Divyansh Mittal

TI__Expert 8710 points

Hi,
I have verified the BT.656 progressive patch at my end and I am able to use DSI with the patch applied on kernel.
Please try using DSI separately without patch, I would expect that may not also work, which would indicate DSI interfacing issues on your setup.

0 Yong Zhang 15 days ago in reply to Divyansh Mittal

TI__Genius 17111 points

Sync on the status.

The requirement from India OEM is that LH need 2x Display in parallel. target is to finish demo with this feature in end of Sep, then present to CAR OEM.

1. DSI. (Please note, there is one converter on this path, DSI -> DSI2CSI chip -> Display)

2. BT656 YUV422 interlaced mode over DPI. (please note, there is one converter on this path, DPI -> DPI2CVBS chip -> Display)

Dear Pengqi.

as discussed yesterday, please follow the suggestion to verify each Display paths individually. TI will support you to fix the problem if any of those doesn't work firstly. then please migrate the two displays together, then check if there is coupling issue.

So would you please help provide current status?

1. if it is ok for DSI only? and what is the modification?

2. if it is ok for BT656 YUV422 interlaced mode over DPI w/ DPI2CVBS also? and what is the modification?

3. if it is ok for both display path when 1 and 2 are finished?

thanks a lot!

yong

0 Wangpq 14 days ago in reply to Divyansh Mittal

Prodigy 221 points

0 Wangpq 14 days ago in reply to Divyansh Mittal

Prodigy 221 points

set "tidss->bt656_enabled = 1;" DSI with no signal.

set "tidss->bt656_enabled = 0;" DSI have signal.

0 Wangpq 14 days ago in reply to Wangpq

Prodigy 221 points

Hi:

The DSI interface display was originally fine, but now with the addition of DPI-BT656 patch, there is no signal at the DSI interface.

then i set "tidss->bt656_enabled = 0;" DSI have signal.

0 Divyansh Mittal 14 days ago in reply to Wangpq

TI__Expert 8710 points

Hi,
Your modification to the patch is incorrect and hence this is expected.

You are making the change "tidss->bt656_enabled = 1;" in DSS driver.
DSS0 and DSS1 probe go through the same tidss_probe function call, and you are essentially hardcoding bt.656 enabled for both DSS0 and DSS1 due to which DSI does not work.

As shared in the original patch, correct way to do this is not by hardcoding, rather go to your DTS files:
1) Within &dss0, add the following flag:

ti,bt656-mode;

2) This flag should not be there in dss1 nodes.
3) Remove your hardcoded bt mode enabler from dss driver.

The following line in tidss_drv.c will take care of reading the flag from dts:

tidss->bt656_enabled = device_property_read_bool(dev, "ti,bt656-mode");

0 Tao Han 7 days ago in reply to Divyansh Mittal

TI__Expert 6465 points

Hi Divyansh:

Based on your suggest just enable DSS0 pipeline BT656 interleave mode, this problem resolved.

Now DSI/DPI can output different resolution video. I will close this ticket.

Best Regards!

Han Tao

0 Donghui Peng 7 days ago in reply to Divyansh Mittal

Prodigy 60 points

my board: AM62P DPI => BT6576 => TP2803 => CVBS panel

I am using the DPI interface on the AM62P board to output BT656 （to CVBS） images,

the displayed picture is showed above.

Do you have the final patch package for BT656 with DPI output.

0 Donghui Peng 6 days ago in reply to Donghui Peng

Prodigy 60 points

diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
index 4f8557d3e..8b83b18c0 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
@@ -12,6 +12,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/net/ti-dp83867.h>
 #include "k3-am62p5.dtsi"
+#include "k3-am62p5-sk-bt656-tp2803fe.dtsi"
 
 / {
 	compatible = "ti,am62p5-sk", "ti,am62p5";
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 3a2f4a9f1..a8f083d8d 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -98,7 +98,6 @@ config DRM_PANEL_LVDS
 config DRM_PANEL_SIMPLE
 	tristate "support for simple panels (other than eDP ones)"
 	depends on OF
-	depends on BACKLIGHT_CLASS_DEVICE
 	depends on PM
 	select VIDEOMODE_HELPERS
 	help
diff --git a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
index 4618c892c..16a03dc64 100644
--- a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
+++ b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
@@ -462,7 +462,7 @@ static int rpi_touchscreen_dsi_probe(struct mipi_dsi_device *dsi)
 			   MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 			   MIPI_DSI_MODE_LPM);
 	dsi->format = MIPI_DSI_FMT_RGB888;
-	dsi->lanes = 1;
+	dsi->lanes = 4;
 
 	ret = mipi_dsi_attach(dsi);
 
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 87055ab3c..7961a6235 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -41,6 +41,9 @@
 #include <drm/drm_mipi_dsi.h>
 #include <drm/drm_panel.h>
 
+#define MSG(fmt, args...) printk(KERN_ERR "\033[35m<panel> "fmt" %s", ##args,"")
+
+
 /**
  * struct panel_desc - Describes a simple panel.
  */
@@ -557,7 +560,6 @@ static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 	int connector_type;
 	u32 bus_flags;
 	int err;
-
 	panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
 	if (!panel)
 		return -ENOMEM;
@@ -711,3938 +713,84 @@ static void panel_simple_shutdown(struct device *dev)
 	drm_panel_unprepare(&panel->base);
 }
 
-static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
-	.clock = 71100,
-	.hdisplay = 1280,
-	.hsync_start = 1280 + 40,
-	.hsync_end = 1280 + 40 + 80,
-	.htotal = 1280 + 40 + 80 + 40,
-	.vdisplay = 800,
-	.vsync_start = 800 + 3,
-	.vsync_end = 800 + 3 + 10,
-	.vtotal = 800 + 3 + 10 + 10,
-	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
-};
-
-static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
-	.modes = &ampire_am_1280800n3tzqw_t00h_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 217,
-		.height = 136,
-	},
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 2,
-	.hsync_end = 480 + 2 + 41,
-	.htotal = 480 + 2 + 41 + 2,
-	.vdisplay = 272,
-	.vsync_start = 272 + 2,
-	.vsync_end = 272 + 2 + 10,
-	.vtotal = 272 + 2 + 10 + 2,
-	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
-};
-
-static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
-	.modes = &ampire_am_480272h3tmqw_t01h_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 99,
-		.height = 58,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-};
-
-static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
-	.clock = 33333,
-	.hdisplay = 800,
-	.hsync_start = 800 + 0,
-	.hsync_end = 800 + 0 + 255,
-	.htotal = 800 + 0 + 255 + 0,
-	.vdisplay = 480,
-	.vsync_start = 480 + 2,
-	.vsync_end = 480 + 2 + 45,
-	.vtotal = 480 + 2 + 45 + 0,
-	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
-};
-
-static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
-	.pixelclock = { 29930000, 33260000, 36590000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 1, 40, 168 },
-	.hback_porch = { 88, 88, 88 },
-	.hsync_len = { 1, 128, 128 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 1, 35, 37 },
-	.vback_porch = { 8, 8, 8 },
-	.vsync_len = { 1, 2, 2 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
-		 DISPLAY_FLAGS_SYNC_POSEDGE,
-};
-
-static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
-	.timings = &ampire_am_800480l1tmqw_t00h_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 111,
-		.height = 67,
+#if 1
+// PAL test
+static const struct drm_display_mode bt656_720x576P25_mode = {
+	.clock = 27000,	// 25fps OK htotal*vtotal*25*2= 27000 Khz
+	.hdisplay    = 720,
+	.hsync_start = 720 + 2,      // hsync_start + vfb1e
+	.hsync_end   = 720 + 2 + 22, // hsync_start + vfb2e
+	.htotal      = 864, 	     // hsync_end   + hback_porch; 864  = > 858
+	.vdisplay    = 576,
+	.vsync_start = 576 + 2,      // vdisplay    + vfb1o;
+	.vsync_end   = 576 + 2 + 23, // vsync_start + vfb2o;
+	.vtotal      = 625,          // vsync_end + vback_porch; PAL:625 ，NTSC:525 
+	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |DRM_MODE_FLAG_INTERLACE,
+};
+#endif
+
+#if 0
+// NTSC  failed
+static const struct drm_display_mode bt656_720x576P25_mode = {
+	.clock = 27000,	// 25fps OK htotal*vtotal*25*2= 27000 Khz
+	.hdisplay    = 720,
+	.hsync_start = 720 + 1,      // hdisplay + hfront_porch;
+	.hsync_end   = 720 + 15,	 // hsync_start 
+	.htotal      = 864, 	     // hsync_end + hback_porch; 864
+	.vdisplay    = 487,
+	.vsync_start = 487 + 10,     // vdisplay + vfront_porch;
+	.vsync_end   = 487 + 10 + 20,// vsync_start + vsync_len;
+	.vtotal      = 525,          // vsync_end + vback_porch; PAL 制式通常为 625 行，NTSC 为 525 行
+	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |DRM_MODE_FLAG_INTERLACE,
+};
+#endif
+
+static const struct panel_desc bt656_PAL = {
+	.modes = &bt656_720x576P25_mode,
+	.num_modes = 1,
+	.bpc = 8,
+	.size = {
+		.width = 129,
+		.height = 86,
 	},
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
-		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
-		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct panel_desc ampire_am800480r3tmqwa1h = {
-	.modes = &ampire_am800480r3tmqwa1h_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-};
-
-static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
-	.pixelclock = { 34500000, 39600000, 50400000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 12, 112, 312 },
-	.hback_porch = { 87, 87, 48 },
-	.hsync_len = { 1, 1, 40 },
-	.vactive = { 600, 600, 600 },
-	.vfront_porch = { 1, 21, 61 },
-	.vback_porch = { 38, 38, 19 },
-	.vsync_len = { 1, 1, 20 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-		DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
-		DISPLAY_FLAGS_SYNC_POSEDGE,
-};
-
-static const struct panel_desc ampire_am800600p5tmqwtb8h = {
-	.timings = &ampire_am800600p5tmqw_tb8h_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 162,
-		.height = 122,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
-		DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
-		DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
+		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
 	.connector_type = DRM_MODE_CONNECTOR_DPI,
 };
 
-static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
-	.pixelclock = { 26400000, 33300000, 46800000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 16, 210, 354 },
-	.hback_porch = { 45, 36, 6 },
-	.hsync_len = { 1, 10, 40 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 7, 22, 147 },
-	.vback_porch = { 22, 13, 3 },
-	.vsync_len = { 1, 10, 20 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-		DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
-};
-
-static const struct panel_desc armadeus_st0700_adapt = {
-	.timings = &santek_st0700i5y_rbslw_f_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
-};
-
-static const struct drm_display_mode auo_b101aw03_mode = {
-	.clock = 51450,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 156,
-	.hsync_end = 1024 + 156 + 8,
-	.htotal = 1024 + 156 + 8 + 156,
-	.vdisplay = 600,
-	.vsync_start = 600 + 16,
-	.vsync_end = 600 + 16 + 6,
-	.vtotal = 600 + 16 + 6 + 16,
-};
-
-static const struct panel_desc auo_b101aw03 = {
-	.modes = &auo_b101aw03_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 223,
-		.height = 125,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode auo_b101xtn01_mode = {
-	.clock = 72000,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 20,
-	.hsync_end = 1366 + 20 + 70,
-	.htotal = 1366 + 20 + 70,
-	.vdisplay = 768,
-	.vsync_start = 768 + 14,
-	.vsync_end = 768 + 14 + 42,
-	.vtotal = 768 + 14 + 42,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc auo_b101xtn01 = {
-	.modes = &auo_b101xtn01_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 223,
-		.height = 125,
-	},
-};
+static const struct drm_display_mode raspberrypi_7inch_mode = {
+	.clock = 56992000/1000, // htotal * vtotal * 50 /(4根线)/1000 *2 /* kmstest 25fps  OK */
+	.hdisplay = 1920,
+	.hsync_start = 1920 + 48,
+	.hsync_end = 1920 + 48 + 32,
+	.htotal = 1920 + 48 + 32 + 80, // 2080
+	.vdisplay = 1080,
+	.vsync_start = 1080 + 3,
+	.vsync_end = 1080 + 3 + 7,
+	.vtotal = 1080 + 3 + 7 + 6, // 1096
 
-static const struct drm_display_mode auo_b116xw03_mode = {
-	.clock = 70589,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 40,
-	.hsync_end = 1366 + 40 + 40,
-	.htotal = 1366 + 40 + 40 + 32,
-	.vdisplay = 768,
-	.vsync_start = 768 + 10,
-	.vsync_end = 768 + 10 + 12,
-	.vtotal = 768 + 10 + 12 + 6,
 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 };
-
-static const struct panel_desc auo_b116xw03 = {
-	.modes = &auo_b116xw03_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 256,
-		.height = 144,
-	},
-	.delay = {
-		.prepare = 1,
-		.enable = 200,
-		.disable = 200,
-		.unprepare = 500,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing auo_g070vvn01_timings = {
-	.pixelclock = { 33300000, 34209000, 45000000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 20, 40, 200 },
-	.hback_porch = { 87, 40, 1 },
-	.hsync_len = { 1, 48, 87 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 5, 13, 200 },
-	.vback_porch = { 31, 31, 29 },
-	.vsync_len = { 1, 1, 3 },
-};
-
-static const struct panel_desc auo_g070vvn01 = {
-	.timings = &auo_g070vvn01_timings,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.delay = {
-		.prepare = 200,
-		.enable = 50,
-		.disable = 50,
-		.unprepare = 1000,
-	},
-};
-
-static const struct drm_display_mode auo_g101evn010_mode = {
-	.clock = 68930,
-	.hdisplay = 1280,
-	.hsync_start = 1280 + 82,
-	.hsync_end = 1280 + 82 + 2,
-	.htotal = 1280 + 82 + 2 + 84,
-	.vdisplay = 800,
-	.vsync_start = 800 + 8,
-	.vsync_end = 800 + 8 + 2,
-	.vtotal = 800 + 8 + 2 + 6,
-};
-
-static const struct panel_desc auo_g101evn010 = {
-	.modes = &auo_g101evn010_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 216,
-		.height = 135,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode auo_g104sn02_mode = {
-	.clock = 40000,
-	.hdisplay = 800,
-	.hsync_start = 800 + 40,
-	.hsync_end = 800 + 40 + 216,
-	.htotal = 800 + 40 + 216 + 128,
-	.vdisplay = 600,
-	.vsync_start = 600 + 10,
-	.vsync_end = 600 + 10 + 35,
-	.vtotal = 600 + 10 + 35 + 2,
-};
-
-static const struct panel_desc auo_g104sn02 = {
-	.modes = &auo_g104sn02_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 211,
-		.height = 158,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing auo_g121ean01_timing = {
-	.pixelclock = { 60000000, 74400000, 90000000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 20, 50, 100 },
-	.hback_porch = { 20, 50, 100 },
-	.hsync_len = { 30, 100, 200 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 2, 10, 25 },
-	.vback_porch = { 2, 10, 25 },
-	.vsync_len = { 4, 18, 50 },
-};
-
-static const struct panel_desc auo_g121ean01 = {
-	.timings = &auo_g121ean01_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 261,
-		.height = 163,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing auo_g133han01_timings = {
-	.pixelclock = { 134000000, 141200000, 149000000 },
-	.hactive = { 1920, 1920, 1920 },
-	.hfront_porch = { 39, 58, 77 },
-	.hback_porch = { 59, 88, 117 },
-	.hsync_len = { 28, 42, 56 },
-	.vactive = { 1080, 1080, 1080 },
-	.vfront_porch = { 3, 8, 11 },
-	.vback_porch = { 5, 14, 19 },
-	.vsync_len = { 4, 14, 19 },
-};
-
-static const struct panel_desc auo_g133han01 = {
-	.timings = &auo_g133han01_timings,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 293,
-		.height = 165,
-	},
-	.delay = {
-		.prepare = 200,
-		.enable = 50,
-		.disable = 50,
-		.unprepare = 1000,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode auo_g156xtn01_mode = {
-	.clock = 76000,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 33,
-	.hsync_end = 1366 + 33 + 67,
-	.htotal = 1560,
-	.vdisplay = 768,
-	.vsync_start = 768 + 4,
-	.vsync_end = 768 + 4 + 4,
-	.vtotal = 806,
-};
-
-static const struct panel_desc auo_g156xtn01 = {
-	.modes = &auo_g156xtn01_mode,
+static const struct panel_desc raspberrypi_7inch = {
+	.modes = &raspberrypi_7inch_mode,
 	.num_modes = 1,
 	.bpc = 8,
-	.size = {
-		.width = 344,
-		.height = 194,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing auo_g185han01_timings = {
-	.pixelclock = { 120000000, 144000000, 175000000 },
-	.hactive = { 1920, 1920, 1920 },
-	.hfront_porch = { 36, 120, 148 },
-	.hback_porch = { 24, 88, 108 },
-	.hsync_len = { 20, 48, 64 },
-	.vactive = { 1080, 1080, 1080 },
-	.vfront_porch = { 6, 10, 40 },
-	.vback_porch = { 2, 5, 20 },
-	.vsync_len = { 2, 5, 20 },
-};
-
-static const struct panel_desc auo_g185han01 = {
-	.timings = &auo_g185han01_timings,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 409,
-		.height = 230,
-	},
-	.delay = {
-		.prepare = 50,
-		.enable = 200,
-		.disable = 110,
-		.unprepare = 1000,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing auo_g190ean01_timings = {
-	.pixelclock = { 90000000, 108000000, 135000000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 126, 184, 1266 },
-	.hback_porch = { 84, 122, 844 },
-	.hsync_len = { 70, 102, 704 },
-	.vactive = { 1024, 1024, 1024 },
-	.vfront_porch = { 4, 26, 76 },
-	.vback_porch = { 2, 8, 25 },
-	.vsync_len = { 2, 8, 25 },
-};
-
-static const struct panel_desc auo_g190ean01 = {
-	.timings = &auo_g190ean01_timings,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 376,
-		.height = 301,
-	},
-	.delay = {
-		.prepare = 50,
-		.enable = 200,
-		.disable = 110,
-		.unprepare = 1000,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing auo_p320hvn03_timings = {
-	.pixelclock = { 106000000, 148500000, 164000000 },
-	.hactive = { 1920, 1920, 1920 },
-	.hfront_porch = { 25, 50, 130 },
-	.hback_porch = { 25, 50, 130 },
-	.hsync_len = { 20, 40, 105 },
-	.vactive = { 1080, 1080, 1080 },
-	.vfront_porch = { 8, 17, 150 },
-	.vback_porch = { 8, 17, 150 },
-	.vsync_len = { 4, 11, 100 },
-};
-
-static const struct panel_desc auo_p320hvn03 = {
-	.timings = &auo_p320hvn03_timings,
-	.num_timings = 1,
-	.bpc = 8,
 	.size = {
 		.width = 698,
 		.height = 393,
 	},
-	.delay = {
-		.prepare = 1,
-		.enable = 450,
-		.unprepare = 500,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode auo_t215hvn01_mode = {
-	.clock = 148800,
-	.hdisplay = 1920,
-	.hsync_start = 1920 + 88,
-	.hsync_end = 1920 + 88 + 44,
-	.htotal = 1920 + 88 + 44 + 148,
-	.vdisplay = 1080,
-	.vsync_start = 1080 + 4,
-	.vsync_end = 1080 + 4 + 5,
-	.vtotal = 1080 + 4 + 5 + 36,
-};
-
-static const struct panel_desc auo_t215hvn01 = {
-	.modes = &auo_t215hvn01_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 430,
-		.height = 270,
-	},
-	.delay = {
-		.disable = 5,
-		.unprepare = 1000,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode avic_tm070ddh03_mode = {
-	.clock = 51200,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 160,
-	.hsync_end = 1024 + 160 + 4,
-	.htotal = 1024 + 160 + 4 + 156,
-	.vdisplay = 600,
-	.vsync_start = 600 + 17,
-	.vsync_end = 600 + 17 + 1,
-	.vtotal = 600 + 17 + 1 + 17,
-};
-
-static const struct panel_desc avic_tm070ddh03 = {
-	.modes = &avic_tm070ddh03_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 154,
-		.height = 90,
-	},
-	.delay = {
-		.prepare = 20,
-		.enable = 200,
-		.disable = 200,
-	},
-};
-
-static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
-	.clock = 30000,
-	.hdisplay = 800,
-	.hsync_start = 800 + 40,
-	.hsync_end = 800 + 40 + 48,
-	.htotal = 800 + 40 + 48 + 40,
-	.vdisplay = 480,
-	.vsync_start = 480 + 13,
-	.vsync_end = 480 + 13 + 3,
-	.vtotal = 480 + 13 + 3 + 29,
-};
-
-static const struct panel_desc bananapi_s070wv20_ct16 = {
-	.modes = &bananapi_s070wv20_ct16_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-};
-
-static const struct display_timing boe_ev121wxm_n10_1850_timing = {
-	.pixelclock = { 69922000, 71000000, 72293000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 48, 48, 48 },
-	.hback_porch = { 80, 80, 80 },
-	.hsync_len = { 32, 32, 32 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 3, 3, 3 },
-	.vback_porch = { 14, 14, 14 },
-	.vsync_len = { 6, 6, 6 },
-};
-
-static const struct panel_desc boe_ev121wxm_n10_1850 = {
-	.timings = &boe_ev121wxm_n10_1850_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 261,
-		.height = 163,
-	},
-	.delay = {
-		.prepare = 9,
-		.enable = 300,
-		.unprepare = 300,
-		.disable = 560,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode boe_hv070wsa_mode = {
-	.clock = 42105,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 30,
-	.hsync_end = 1024 + 30 + 30,
-	.htotal = 1024 + 30 + 30 + 30,
-	.vdisplay = 600,
-	.vsync_start = 600 + 10,
-	.vsync_end = 600 + 10 + 10,
-	.vtotal = 600 + 10 + 10 + 10,
-};
-
-static const struct panel_desc boe_hv070wsa = {
-	.modes = &boe_hv070wsa_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 154,
-		.height = 90,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 5,
-	.hsync_end = 480 + 5 + 5,
-	.htotal = 480 + 5 + 5 + 40,
-	.vdisplay = 272,
-	.vsync_start = 272 + 8,
-	.vsync_end = 272 + 8 + 8,
-	.vtotal = 272 + 8 + 8 + 8,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
-
-static const struct panel_desc cdtech_s043wq26h_ct7 = {
-	.modes = &cdtech_s043wq26h_ct7_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 95,
-		.height = 54,
-	},
-	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
-};
-
-/* S070PWS19HP-FC21 2017/04/22 */
-static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
-	.clock = 51200,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 160,
-	.hsync_end = 1024 + 160 + 20,
-	.htotal = 1024 + 160 + 20 + 140,
-	.vdisplay = 600,
-	.vsync_start = 600 + 12,
-	.vsync_end = 600 + 12 + 3,
-	.vtotal = 600 + 12 + 3 + 20,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
-
-static const struct panel_desc cdtech_s070pws19hp_fc21 = {
-	.modes = &cdtech_s070pws19hp_fc21_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-/* S070SWV29HG-DC44 2017/09/21 */
-static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
-	.clock = 33300,
-	.hdisplay = 800,
-	.hsync_start = 800 + 210,
-	.hsync_end = 800 + 210 + 2,
-	.htotal = 800 + 210 + 2 + 44,
-	.vdisplay = 480,
-	.vsync_start = 480 + 22,
-	.vsync_end = 480 + 22 + 2,
-	.vtotal = 480 + 22 + 2 + 21,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
-
-static const struct panel_desc cdtech_s070swv29hg_dc44 = {
-	.modes = &cdtech_s070swv29hg_dc44_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
-	.clock = 35000,
-	.hdisplay = 800,
-	.hsync_start = 800 + 40,
-	.hsync_end = 800 + 40 + 40,
-	.htotal = 800 + 40 + 40 + 48,
-	.vdisplay = 480,
-	.vsync_start = 480 + 29,
-	.vsync_end = 480 + 29 + 13,
-	.vtotal = 480 + 29 + 13 + 3,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
-
-static const struct panel_desc cdtech_s070wv95_ct16 = {
-	.modes = &cdtech_s070wv95_ct16_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 154,
-		.height = 85,
-	},
-};
-
-static const struct display_timing chefree_ch101olhlwh_002_timing = {
-	.pixelclock = { 68900000, 71100000, 73400000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 65, 80, 95 },
-	.hback_porch = { 64, 79, 94 },
-	.hsync_len = { 1, 1, 1 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 7, 11, 14 },
-	.vback_porch = { 7, 11, 14 },
-	.vsync_len = { 1, 1, 1 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc chefree_ch101olhlwh_002 = {
-	.timings = &chefree_ch101olhlwh_002_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 217,
-		.height = 135,
-	},
-	.delay = {
-		.enable = 200,
-		.disable = 200,
-	},
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
-	.clock = 66770,
-	.hdisplay = 800,
-	.hsync_start = 800 + 49,
-	.hsync_end = 800 + 49 + 33,
-	.htotal = 800 + 49 + 33 + 17,
-	.vdisplay = 1280,
-	.vsync_start = 1280 + 1,
-	.vsync_end = 1280 + 1 + 7,
-	.vtotal = 1280 + 1 + 7 + 15,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc chunghwa_claa070wp03xg = {
-	.modes = &chunghwa_claa070wp03xg_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 94,
-		.height = 150,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
-	.clock = 72070,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 58,
-	.hsync_end = 1366 + 58 + 58,
-	.htotal = 1366 + 58 + 58 + 58,
-	.vdisplay = 768,
-	.vsync_start = 768 + 4,
-	.vsync_end = 768 + 4 + 4,
-	.vtotal = 768 + 4 + 4 + 4,
-};
-
-static const struct panel_desc chunghwa_claa101wa01a = {
-	.modes = &chunghwa_claa101wa01a_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 220,
-		.height = 120,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode chunghwa_claa101wb01_mode = {
-	.clock = 69300,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 48,
-	.hsync_end = 1366 + 48 + 32,
-	.htotal = 1366 + 48 + 32 + 20,
-	.vdisplay = 768,
-	.vsync_start = 768 + 16,
-	.vsync_end = 768 + 16 + 8,
-	.vtotal = 768 + 16 + 8 + 16,
-};
-
-static const struct panel_desc chunghwa_claa101wb01 = {
-	.modes = &chunghwa_claa101wb01_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 223,
-		.height = 125,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing dataimage_fg040346dsswbg04_timing = {
-	.pixelclock = { 5000000, 9000000, 12000000 },
-	.hactive = { 480, 480, 480 },
-	.hfront_porch = { 12, 12, 12 },
-	.hback_porch = { 12, 12, 12 },
-	.hsync_len = { 21, 21, 21 },
-	.vactive = { 272, 272, 272 },
-	.vfront_porch = { 4, 4, 4 },
-	.vback_porch = { 4, 4, 4 },
-	.vsync_len = { 8, 8, 8 },
-};
-
-static const struct panel_desc dataimage_fg040346dsswbg04 = {
-	.timings = &dataimage_fg040346dsswbg04_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 95,
-		.height = 54,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
-	.pixelclock = { 68900000, 71110000, 73400000 },
-	.hactive = { 1280, 1280, 1280 },
-	.vactive = { 800, 800, 800 },
-	.hback_porch = { 100, 100, 100 },
-	.hfront_porch = { 100, 100, 100 },
-	.vback_porch = { 5, 5, 5 },
-	.vfront_porch = { 5, 5, 5 },
-	.hsync_len = { 24, 24, 24 },
-	.vsync_len = { 3, 3, 3 },
-	.flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
-		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
-};
-
-static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
-	.timings = &dataimage_fg1001l0dsswmg01_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 217,
-		.height = 136,
-	},
-};
-
-static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
-	.clock = 33260,
-	.hdisplay = 800,
-	.hsync_start = 800 + 40,
-	.hsync_end = 800 + 40 + 128,
-	.htotal = 800 + 40 + 128 + 88,
-	.vdisplay = 480,
-	.vsync_start = 480 + 10,
-	.vsync_end = 480 + 10 + 2,
-	.vtotal = 480 + 10 + 2 + 33,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc dataimage_scf0700c48ggu18 = {
-	.modes = &dataimage_scf0700c48ggu18_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
-};
-
-static const struct display_timing dlc_dlc0700yzg_1_timing = {
-	.pixelclock = { 45000000, 51200000, 57000000 },
-	.hactive = { 1024, 1024, 1024 },
-	.hfront_porch = { 100, 106, 113 },
-	.hback_porch = { 100, 106, 113 },
-	.hsync_len = { 100, 108, 114 },
-	.vactive = { 600, 600, 600 },
-	.vfront_porch = { 8, 11, 15 },
-	.vback_porch = { 8, 11, 15 },
-	.vsync_len = { 9, 13, 15 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc dlc_dlc0700yzg_1 = {
-	.timings = &dlc_dlc0700yzg_1_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-	.delay = {
-		.prepare = 30,
-		.enable = 200,
-		.disable = 200,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing dlc_dlc1010gig_timing = {
-	.pixelclock = { 68900000, 71100000, 73400000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 43, 53, 63 },
-	.hback_porch = { 43, 53, 63 },
-	.hsync_len = { 44, 54, 64 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 5, 8, 11 },
-	.vback_porch = { 5, 8, 11 },
-	.vsync_len = { 5, 7, 11 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc dlc_dlc1010gig = {
-	.timings = &dlc_dlc1010gig_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 216,
-		.height = 135,
-	},
-	.delay = {
-		.prepare = 60,
-		.enable = 150,
-		.disable = 100,
-		.unprepare = 60,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode edt_et035012dm6_mode = {
-	.clock = 6500,
-	.hdisplay = 320,
-	.hsync_start = 320 + 20,
-	.hsync_end = 320 + 20 + 30,
-	.htotal = 320 + 20 + 68,
-	.vdisplay = 240,
-	.vsync_start = 240 + 4,
-	.vsync_end = 240 + 4 + 4,
-	.vtotal = 240 + 4 + 4 + 14,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc edt_et035012dm6 = {
-	.modes = &edt_et035012dm6_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 70,
-		.height = 52,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
-};
-
-static const struct drm_display_mode edt_etm0350g0dh6_mode = {
-	.clock = 6520,
-	.hdisplay = 320,
-	.hsync_start = 320 + 20,
-	.hsync_end = 320 + 20 + 68,
-	.htotal = 320 + 20 + 68,
-	.vdisplay = 240,
-	.vsync_start = 240 + 4,
-	.vsync_end = 240 + 4 + 18,
-	.vtotal = 240 + 4 + 18,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc edt_etm0350g0dh6 = {
-	.modes = &edt_etm0350g0dh6_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 70,
-		.height = 53,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode edt_etm043080dh6gp_mode = {
-	.clock = 10870,
-	.hdisplay = 480,
-	.hsync_start = 480 + 8,
-	.hsync_end = 480 + 8 + 4,
-	.htotal = 480 + 8 + 4 + 41,
-
-	/*
-	 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
-	 * fb_align
-	 */
-
-	.vdisplay = 288,
-	.vsync_start = 288 + 2,
-	.vsync_end = 288 + 2 + 4,
-	.vtotal = 288 + 2 + 4 + 10,
-};
-
-static const struct panel_desc edt_etm043080dh6gp = {
-	.modes = &edt_etm043080dh6gp_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 100,
-		.height = 65,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode edt_etm0430g0dh6_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 2,
-	.hsync_end = 480 + 2 + 41,
-	.htotal = 480 + 2 + 41 + 2,
-	.vdisplay = 272,
-	.vsync_start = 272 + 2,
-	.vsync_end = 272 + 2 + 10,
-	.vtotal = 272 + 2 + 10 + 2,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
-
-static const struct panel_desc edt_etm0430g0dh6 = {
-	.modes = &edt_etm0430g0dh6_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 95,
-		.height = 54,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode edt_et057090dhu_mode = {
-	.clock = 25175,
-	.hdisplay = 640,
-	.hsync_start = 640 + 16,
-	.hsync_end = 640 + 16 + 30,
-	.htotal = 640 + 16 + 30 + 114,
-	.vdisplay = 480,
-	.vsync_start = 480 + 10,
-	.vsync_end = 480 + 10 + 3,
-	.vtotal = 480 + 10 + 3 + 32,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc edt_et057090dhu = {
-	.modes = &edt_et057090dhu_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 115,
-		.height = 86,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode edt_etm0700g0dh6_mode = {
-	.clock = 33260,
-	.hdisplay = 800,
-	.hsync_start = 800 + 40,
-	.hsync_end = 800 + 40 + 128,
-	.htotal = 800 + 40 + 128 + 88,
-	.vdisplay = 480,
-	.vsync_start = 480 + 10,
-	.vsync_end = 480 + 10 + 2,
-	.vtotal = 480 + 10 + 2 + 33,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
-
-static const struct panel_desc edt_etm0700g0dh6 = {
-	.modes = &edt_etm0700g0dh6_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct panel_desc edt_etm0700g0bdh6 = {
-	.modes = &edt_etm0700g0dh6_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct display_timing edt_etml0700y5dha_timing = {
-	.pixelclock = { 40800000, 51200000, 67200000 },
-	.hactive = { 1024, 1024, 1024 },
-	.hfront_porch = { 30, 106, 125 },
-	.hback_porch = { 30, 106, 125 },
-	.hsync_len = { 30, 108, 126 },
-	.vactive = { 600, 600, 600 },
-	.vfront_porch = { 3, 12, 67},
-	.vback_porch = { 3, 12, 67 },
-	.vsync_len = { 4, 11, 66 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-		 DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc edt_etml0700y5dha = {
-	.timings = &edt_etml0700y5dha_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 155,
-		.height = 86,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode edt_etmv570g2dhu_mode = {
-	.clock = 25175,
-	.hdisplay = 640,
-	.hsync_start = 640,
-	.hsync_end = 640 + 16,
-	.htotal = 640 + 16 + 30 + 114,
-	.vdisplay = 480,
-	.vsync_start = 480 + 10,
-	.vsync_end = 480 + 10 + 3,
-	.vtotal = 480 + 10 + 3 + 35,
-	.flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
-};
-
-static const struct panel_desc edt_etmv570g2dhu = {
-	.modes = &edt_etmv570g2dhu_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 115,
-		.height = 86,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct display_timing eink_vb3300_kca_timing = {
-	.pixelclock = { 40000000, 40000000, 40000000 },
-	.hactive = { 334, 334, 334 },
-	.hfront_porch = { 1, 1, 1 },
-	.hback_porch = { 1, 1, 1 },
-	.hsync_len = { 1, 1, 1 },
-	.vactive = { 1405, 1405, 1405 },
-	.vfront_porch = { 1, 1, 1 },
-	.vback_porch = { 1, 1, 1 },
-	.vsync_len = { 1, 1, 1 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
-};
-
-static const struct panel_desc eink_vb3300_kca = {
-	.timings = &eink_vb3300_kca_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 157,
-		.height = 209,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct display_timing evervision_vgg804821_timing = {
-	.pixelclock = { 27600000, 33300000, 50000000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 40, 66, 70 },
-	.hback_porch = { 40, 67, 70 },
-	.hsync_len = { 40, 67, 70 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 6, 10, 10 },
-	.vback_porch = { 7, 11, 11 },
-	.vsync_len = { 7, 11, 11 },
-	.flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
-		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
-		 DISPLAY_FLAGS_SYNC_NEGEDGE,
-};
-
-static const struct panel_desc evervision_vgg804821 = {
-	.timings = &evervision_vgg804821_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 108,
-		.height = 64,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
-};
-
-static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
-	.clock = 32260,
-	.hdisplay = 800,
-	.hsync_start = 800 + 168,
-	.hsync_end = 800 + 168 + 64,
-	.htotal = 800 + 168 + 64 + 88,
-	.vdisplay = 480,
-	.vsync_start = 480 + 37,
-	.vsync_end = 480 + 37 + 2,
-	.vtotal = 480 + 37 + 2 + 8,
-};
-
-static const struct panel_desc foxlink_fl500wvr00_a0t = {
-	.modes = &foxlink_fl500wvr00_a0t_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 108,
-		.height = 65,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-};
-
-static const struct drm_display_mode frida_frd350h54004_modes[] = {
-	{ /* 60 Hz */
-		.clock = 6000,
-		.hdisplay = 320,
-		.hsync_start = 320 + 44,
-		.hsync_end = 320 + 44 + 16,
-		.htotal = 320 + 44 + 16 + 20,
-		.vdisplay = 240,
-		.vsync_start = 240 + 2,
-		.vsync_end = 240 + 2 + 6,
-		.vtotal = 240 + 2 + 6 + 2,
-		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-	},
-	{ /* 50 Hz */
-		.clock = 5400,
-		.hdisplay = 320,
-		.hsync_start = 320 + 56,
-		.hsync_end = 320 + 56 + 16,
-		.htotal = 320 + 56 + 16 + 40,
-		.vdisplay = 240,
-		.vsync_start = 240 + 2,
-		.vsync_end = 240 + 2 + 6,
-		.vtotal = 240 + 2 + 6 + 2,
-		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-	},
-};
-
-static const struct panel_desc frida_frd350h54004 = {
-	.modes = frida_frd350h54004_modes,
-	.num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
-	.bpc = 8,
-	.size = {
-		.width = 77,
-		.height = 64,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode friendlyarm_hd702e_mode = {
-	.clock		= 67185,
-	.hdisplay	= 800,
-	.hsync_start	= 800 + 20,
-	.hsync_end	= 800 + 20 + 24,
-	.htotal		= 800 + 20 + 24 + 20,
-	.vdisplay	= 1280,
-	.vsync_start	= 1280 + 4,
-	.vsync_end	= 1280 + 4 + 8,
-	.vtotal		= 1280 + 4 + 8 + 4,
-	.flags		= DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc friendlyarm_hd702e = {
-	.modes = &friendlyarm_hd702e_mode,
-	.num_modes = 1,
-	.size = {
-		.width	= 94,
-		.height	= 151,
-	},
-};
-
-static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 5,
-	.hsync_end = 480 + 5 + 1,
-	.htotal = 480 + 5 + 1 + 40,
-	.vdisplay = 272,
-	.vsync_start = 272 + 8,
-	.vsync_end = 272 + 8 + 1,
-	.vtotal = 272 + 8 + 1 + 8,
-};
-
-static const struct panel_desc giantplus_gpg482739qs5 = {
-	.modes = &giantplus_gpg482739qs5_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 95,
-		.height = 54,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-};
-
-static const struct display_timing giantplus_gpm940b0_timing = {
-	.pixelclock = { 13500000, 27000000, 27500000 },
-	.hactive = { 320, 320, 320 },
-	.hfront_porch = { 14, 686, 718 },
-	.hback_porch = { 50, 70, 255 },
-	.hsync_len = { 1, 1, 1 },
-	.vactive = { 240, 240, 240 },
-	.vfront_porch = { 1, 1, 179 },
-	.vback_porch = { 1, 21, 31 },
-	.vsync_len = { 1, 1, 6 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
-};
-
-static const struct panel_desc giantplus_gpm940b0 = {
-	.timings = &giantplus_gpm940b0_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 60,
-		.height = 45,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_3X8,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
-};
-
-static const struct display_timing hannstar_hsd070pww1_timing = {
-	.pixelclock = { 64300000, 71100000, 82000000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 1, 1, 10 },
-	.hback_porch = { 1, 1, 10 },
-	/*
-	 * According to the data sheet, the minimum horizontal blanking interval
-	 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
-	 * minimum working horizontal blanking interval to be 60 clocks.
-	 */
-	.hsync_len = { 58, 158, 661 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 1, 1, 10 },
-	.vback_porch = { 1, 1, 10 },
-	.vsync_len = { 1, 21, 203 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc hannstar_hsd070pww1 = {
-	.timings = &hannstar_hsd070pww1_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 151,
-		.height = 94,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing hannstar_hsd100pxn1_timing = {
-	.pixelclock = { 55000000, 65000000, 75000000 },
-	.hactive = { 1024, 1024, 1024 },
-	.hfront_porch = { 40, 40, 40 },
-	.hback_porch = { 220, 220, 220 },
-	.hsync_len = { 20, 60, 100 },
-	.vactive = { 768, 768, 768 },
-	.vfront_porch = { 7, 7, 7 },
-	.vback_porch = { 21, 21, 21 },
-	.vsync_len = { 10, 10, 10 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc hannstar_hsd100pxn1 = {
-	.timings = &hannstar_hsd100pxn1_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 203,
-		.height = 152,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing hannstar_hsd101pww2_timing = {
-	.pixelclock = { 64300000, 71100000, 82000000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 1, 1, 10 },
-	.hback_porch = { 1, 1, 10 },
-	.hsync_len = { 58, 158, 661 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 1, 1, 10 },
-	.vback_porch = { 1, 1, 10 },
-	.vsync_len = { 1, 21, 203 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc hannstar_hsd101pww2 = {
-	.timings = &hannstar_hsd101pww2_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 217,
-		.height = 136,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
-	.clock = 33333,
-	.hdisplay = 800,
-	.hsync_start = 800 + 85,
-	.hsync_end = 800 + 85 + 86,
-	.htotal = 800 + 85 + 86 + 85,
-	.vdisplay = 480,
-	.vsync_start = 480 + 16,
-	.vsync_end = 480 + 16 + 13,
-	.vtotal = 480 + 16 + 13 + 16,
-};
-
-static const struct panel_desc hitachi_tx23d38vm0caa = {
-	.modes = &hitachi_tx23d38vm0caa_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 195,
-		.height = 117,
-	},
-	.delay = {
-		.enable = 160,
-		.disable = 160,
-	},
-};
-
-static const struct drm_display_mode innolux_at043tn24_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 2,
-	.hsync_end = 480 + 2 + 41,
-	.htotal = 480 + 2 + 41 + 2,
-	.vdisplay = 272,
-	.vsync_start = 272 + 2,
-	.vsync_end = 272 + 2 + 10,
-	.vtotal = 272 + 2 + 10 + 2,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
-
-static const struct panel_desc innolux_at043tn24 = {
-	.modes = &innolux_at043tn24_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 95,
-		.height = 54,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
-};
-
-static const struct drm_display_mode innolux_at070tn92_mode = {
-	.clock = 33333,
-	.hdisplay = 800,
-	.hsync_start = 800 + 210,
-	.hsync_end = 800 + 210 + 20,
-	.htotal = 800 + 210 + 20 + 46,
-	.vdisplay = 480,
-	.vsync_start = 480 + 22,
-	.vsync_end = 480 + 22 + 10,
-	.vtotal = 480 + 22 + 23 + 10,
-};
-
-static const struct panel_desc innolux_at070tn92 = {
-	.modes = &innolux_at070tn92_mode,
-	.num_modes = 1,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-};
-
-static const struct display_timing innolux_g070ace_l01_timing = {
-	.pixelclock = { 25200000, 35000000, 35700000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 30, 32, 87 },
-	.hback_porch = { 30, 32, 87 },
-	.hsync_len = { 1, 1, 1 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 3, 3, 3 },
-	.vback_porch = { 13, 13, 13 },
-	.vsync_len = { 1, 1, 4 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc innolux_g070ace_l01 = {
-	.timings = &innolux_g070ace_l01_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.delay = {
-		.prepare = 10,
-		.enable = 50,
-		.disable = 50,
-		.unprepare = 500,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing innolux_g070y2_l01_timing = {
-	.pixelclock = { 28000000, 29500000, 32000000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 61, 91, 141 },
-	.hback_porch = { 60, 90, 140 },
-	.hsync_len = { 12, 12, 12 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 4, 9, 30 },
-	.vback_porch = { 4, 8, 28 },
-	.vsync_len = { 2, 2, 2 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc innolux_g070y2_l01 = {
-	.timings = &innolux_g070y2_l01_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.delay = {
-		.prepare = 10,
-		.enable = 100,
-		.disable = 100,
-		.unprepare = 800,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode innolux_g070y2_t02_mode = {
-	.clock = 33333,
-	.hdisplay = 800,
-	.hsync_start = 800 + 210,
-	.hsync_end = 800 + 210 + 20,
-	.htotal = 800 + 210 + 20 + 46,
-	.vdisplay = 480,
-	.vsync_start = 480 + 22,
-	.vsync_end = 480 + 22 + 10,
-	.vtotal = 480 + 22 + 23 + 10,
-};
-
-static const struct panel_desc innolux_g070y2_t02 = {
-	.modes = &innolux_g070y2_t02_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 152,
-		.height = 92,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct display_timing innolux_g101ice_l01_timing = {
-	.pixelclock = { 60400000, 71100000, 74700000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 30, 60, 70 },
-	.hback_porch = { 30, 60, 70 },
-	.hsync_len = { 22, 40, 60 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 3, 8, 14 },
-	.vback_porch = { 3, 8, 14 },
-	.vsync_len = { 4, 7, 12 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc innolux_g101ice_l01 = {
-	.timings = &innolux_g101ice_l01_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 217,
-		.height = 135,
-	},
-	.delay = {
-		.enable = 200,
-		.disable = 200,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing innolux_g121i1_l01_timing = {
-	.pixelclock = { 67450000, 71000000, 74550000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 40, 80, 160 },
-	.hback_porch = { 39, 79, 159 },
-	.hsync_len = { 1, 1, 1 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 5, 11, 100 },
-	.vback_porch = { 4, 11, 99 },
-	.vsync_len = { 1, 1, 1 },
-};
-
-static const struct panel_desc innolux_g121i1_l01 = {
-	.timings = &innolux_g121i1_l01_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 261,
-		.height = 163,
-	},
-	.delay = {
-		.enable = 200,
-		.disable = 20,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode innolux_g121x1_l03_mode = {
-	.clock = 65000,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 0,
-	.hsync_end = 1024 + 1,
-	.htotal = 1024 + 0 + 1 + 320,
-	.vdisplay = 768,
-	.vsync_start = 768 + 38,
-	.vsync_end = 768 + 38 + 1,
-	.vtotal = 768 + 38 + 1 + 0,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
-
-static const struct panel_desc innolux_g121x1_l03 = {
-	.modes = &innolux_g121x1_l03_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 246,
-		.height = 185,
-	},
-	.delay = {
-		.enable = 200,
-		.unprepare = 200,
-		.disable = 400,
-	},
-};
-
-static const struct display_timing innolux_g156hce_l01_timings = {
-	.pixelclock = { 120000000, 141860000, 150000000 },
-	.hactive = { 1920, 1920, 1920 },
-	.hfront_porch = { 80, 90, 100 },
-	.hback_porch = { 80, 90, 100 },
-	.hsync_len = { 20, 30, 30 },
-	.vactive = { 1080, 1080, 1080 },
-	.vfront_porch = { 3, 10, 20 },
-	.vback_porch = { 3, 10, 20 },
-	.vsync_len = { 4, 10, 10 },
-};
-
-static const struct panel_desc innolux_g156hce_l01 = {
-	.timings = &innolux_g156hce_l01_timings,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 344,
-		.height = 194,
-	},
-	.delay = {
-		.prepare = 1,		/* T1+T2 */
-		.enable = 450,		/* T5 */
-		.disable = 200,		/* T6 */
-		.unprepare = 10,	/* T3+T7 */
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode innolux_n156bge_l21_mode = {
-	.clock = 69300,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 16,
-	.hsync_end = 1366 + 16 + 34,
-	.htotal = 1366 + 16 + 34 + 50,
-	.vdisplay = 768,
-	.vsync_start = 768 + 2,
-	.vsync_end = 768 + 2 + 6,
-	.vtotal = 768 + 2 + 6 + 12,
-};
-
-static const struct panel_desc innolux_n156bge_l21 = {
-	.modes = &innolux_n156bge_l21_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 344,
-		.height = 193,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode innolux_zj070na_01p_mode = {
-	.clock = 51501,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 128,
-	.hsync_end = 1024 + 128 + 64,
-	.htotal = 1024 + 128 + 64 + 128,
-	.vdisplay = 600,
-	.vsync_start = 600 + 16,
-	.vsync_end = 600 + 16 + 4,
-	.vtotal = 600 + 16 + 4 + 16,
-};
-
-static const struct panel_desc innolux_zj070na_01p = {
-	.modes = &innolux_zj070na_01p_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 154,
-		.height = 90,
-	},
-};
-
-static const struct display_timing koe_tx14d24vm1bpa_timing = {
-	.pixelclock = { 5580000, 5850000, 6200000 },
-	.hactive = { 320, 320, 320 },
-	.hfront_porch = { 30, 30, 30 },
-	.hback_porch = { 30, 30, 30 },
-	.hsync_len = { 1, 5, 17 },
-	.vactive = { 240, 240, 240 },
-	.vfront_porch = { 6, 6, 6 },
-	.vback_porch = { 5, 5, 5 },
-	.vsync_len = { 1, 2, 11 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc koe_tx14d24vm1bpa = {
-	.timings = &koe_tx14d24vm1bpa_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 115,
-		.height = 86,
-	},
-};
-
-static const struct display_timing koe_tx26d202vm0bwa_timing = {
-	.pixelclock = { 151820000, 156720000, 159780000 },
-	.hactive = { 1920, 1920, 1920 },
-	.hfront_porch = { 105, 130, 142 },
-	.hback_porch = { 45, 70, 82 },
-	.hsync_len = { 30, 30, 30 },
-	.vactive = { 1200, 1200, 1200},
-	.vfront_porch = { 3, 5, 10 },
-	.vback_porch = { 2, 5, 10 },
-	.vsync_len = { 5, 5, 5 },
-};
-
-static const struct panel_desc koe_tx26d202vm0bwa = {
-	.timings = &koe_tx26d202vm0bwa_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 217,
-		.height = 136,
-	},
-	.delay = {
-		.prepare = 1000,
-		.enable = 1000,
-		.unprepare = 1000,
-		.disable = 1000,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing koe_tx31d200vm0baa_timing = {
-	.pixelclock = { 39600000, 43200000, 48000000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 16, 36, 56 },
-	.hback_porch = { 16, 36, 56 },
-	.hsync_len = { 8, 8, 8 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 6, 21, 33 },
-	.vback_porch = { 6, 21, 33 },
-	.vsync_len = { 8, 8, 8 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc koe_tx31d200vm0baa = {
-	.timings = &koe_tx31d200vm0baa_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 292,
-		.height = 109,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing kyo_tcg121xglp_timing = {
-	.pixelclock = { 52000000, 65000000, 71000000 },
-	.hactive = { 1024, 1024, 1024 },
-	.hfront_porch = { 2, 2, 2 },
-	.hback_porch = { 2, 2, 2 },
-	.hsync_len = { 86, 124, 244 },
-	.vactive = { 768, 768, 768 },
-	.vfront_porch = { 2, 2, 2 },
-	.vback_porch = { 2, 2, 2 },
-	.vsync_len = { 6, 34, 73 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc kyo_tcg121xglp = {
-	.timings = &kyo_tcg121xglp_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 246,
-		.height = 184,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
-	.clock = 7000,
-	.hdisplay = 320,
-	.hsync_start = 320 + 20,
-	.hsync_end = 320 + 20 + 30,
-	.htotal = 320 + 20 + 30 + 38,
-	.vdisplay = 240,
-	.vsync_start = 240 + 4,
-	.vsync_end = 240 + 4 + 3,
-	.vtotal = 240 + 4 + 3 + 15,
-};
-
-static const struct panel_desc lemaker_bl035_rgb_002 = {
-	.modes = &lemaker_bl035_rgb_002_mode,
-	.num_modes = 1,
-	.size = {
-		.width = 70,
-		.height = 52,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_LOW,
-};
-
-static const struct drm_display_mode lg_lb070wv8_mode = {
-	.clock = 33246,
-	.hdisplay = 800,
-	.hsync_start = 800 + 88,
-	.hsync_end = 800 + 88 + 80,
-	.htotal = 800 + 88 + 80 + 88,
-	.vdisplay = 480,
-	.vsync_start = 480 + 10,
-	.vsync_end = 480 + 10 + 25,
-	.vtotal = 480 + 10 + 25 + 10,
-};
-
-static const struct panel_desc lg_lb070wv8 = {
-	.modes = &lg_lb070wv8_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 151,
-		.height = 91,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode lincolntech_lcd185_101ct_mode = {
-	.clock = 155127,
-	.hdisplay = 1920,
-	.hsync_start = 1920 + 128,
-	.hsync_end = 1920 + 128 + 20,
-	.htotal = 1920 + 128 + 20 + 12,
-	.vdisplay = 1200,
-	.vsync_start = 1200 + 19,
-	.vsync_end = 1200 + 19 + 4,
-	.vtotal = 1200 + 19 + 4 + 20,
-};
-
-static const struct panel_desc lincolntech_lcd185_101ct = {
-	.modes = &lincolntech_lcd185_101ct_mode,
-	.bpc = 8,
-	.num_modes = 1,
-	.size = {
-		.width = 217,
-		.height = 136,
-	},
-	.delay = {
-		.prepare = 50,
-		.disable = 50,
-	},
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing logictechno_lt161010_2nh_timing = {
-	.pixelclock = { 26400000, 33300000, 46800000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 16, 210, 354 },
-	.hback_porch = { 46, 46, 46 },
-	.hsync_len = { 1, 20, 40 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 7, 22, 147 },
-	.vback_porch = { 23, 23, 23 },
-	.vsync_len = { 1, 10, 20 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
-		 DISPLAY_FLAGS_SYNC_POSEDGE,
-};
-
-static const struct panel_desc logictechno_lt161010_2nh = {
-	.timings = &logictechno_lt161010_2nh_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
-		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
-		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct display_timing logictechno_lt170410_2whc_timing = {
-	.pixelclock = { 68900000, 71100000, 73400000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 23, 60, 71 },
-	.hback_porch = { 23, 60, 71 },
-	.hsync_len = { 15, 40, 47 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 5, 7, 10 },
-	.vback_porch = { 5, 7, 10 },
-	.vsync_len = { 6, 9, 12 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
-		 DISPLAY_FLAGS_SYNC_POSEDGE,
-};
-
-static const struct panel_desc logictechno_lt170410_2whc = {
-	.timings = &logictechno_lt170410_2whc_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 217,
-		.height = 136,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
-	.clock = 33000,
-	.hdisplay = 800,
-	.hsync_start = 800 + 112,
-	.hsync_end = 800 + 112 + 3,
-	.htotal = 800 + 112 + 3 + 85,
-	.vdisplay = 480,
-	.vsync_start = 480 + 38,
-	.vsync_end = 480 + 38 + 3,
-	.vtotal = 480 + 38 + 3 + 29,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc logictechno_lttd800480070_l2rt = {
-	.modes = &logictechno_lttd800480070_l2rt_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-	.delay = {
-		.prepare = 45,
-		.enable = 100,
-		.disable = 100,
-		.unprepare = 45
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
-	.clock = 33000,
-	.hdisplay = 800,
-	.hsync_start = 800 + 154,
-	.hsync_end = 800 + 154 + 3,
-	.htotal = 800 + 154 + 3 + 43,
-	.vdisplay = 480,
-	.vsync_start = 480 + 47,
-	.vsync_end = 480 + 47 + 3,
-	.vtotal = 480 + 47 + 3 + 20,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
-	.modes = &logictechno_lttd800480070_l6wh_rt_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-	.delay = {
-		.prepare = 45,
-		.enable = 100,
-		.disable = 100,
-		.unprepare = 45
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode logicpd_type_28_mode = {
-	.clock = 9107,
-	.hdisplay = 480,
-	.hsync_start = 480 + 3,
-	.hsync_end = 480 + 3 + 42,
-	.htotal = 480 + 3 + 42 + 2,
-
-	.vdisplay = 272,
-	.vsync_start = 272 + 2,
-	.vsync_end = 272 + 2 + 11,
-	.vtotal = 272 + 2 + 11 + 3,
-	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
-};
-
-static const struct panel_desc logicpd_type_28 = {
-	.modes = &logicpd_type_28_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 105,
-		.height = 67,
-	},
-	.delay = {
-		.prepare = 200,
-		.enable = 200,
-		.unprepare = 200,
-		.disable = 200,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
-		     DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = {
-	.clock = 150275,
-	.hdisplay = 1920,
-	.hsync_start = 1920 + 32,
-	.hsync_end = 1920 + 32 + 52,
-	.htotal = 1920 + 32 + 52 + 24,
-	.vdisplay = 1200,
-	.vsync_start = 1200 + 24,
-	.vsync_end = 1200 + 24 + 8,
-	.vtotal = 1200 + 24 + 8 + 3,
-};
-
-static const struct panel_desc microtips_mf_101hiebcaf0_c = {
-	.modes = &microtips_mf_101hiebcaf0_c_mode,
-	.bpc = 8,
-	.num_modes = 1,
-	.size = {
-		.width = 217,
-		.height = 136,
-	},
-	.delay = {
-		.prepare = 50,
-		.disable = 50,
-	},
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = {
-	.clock = 93301,
-	.hdisplay = 1920,
-	.hsync_start = 1920 + 72,
-	.hsync_end = 1920 + 72 + 72,
-	.htotal = 1920 + 72 + 72 + 72,
-	.vdisplay = 720,
-	.vsync_start = 720 + 3,
-	.vsync_end = 720 + 3 + 3,
-	.vtotal = 720 + 3 + 3 + 2,
-};
-
-static const struct panel_desc microtips_mf_103hieb0ga0 = {
-	.modes = &microtips_mf_103hieb0ga0_mode,
-	.bpc = 8,
-	.num_modes = 1,
-	.size = {
-		.width = 244,
-		.height = 92,
-	},
-	.delay = {
-		.prepare = 50,
-		.disable = 50,
-	},
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
-	.clock = 30400,
-	.hdisplay = 800,
-	.hsync_start = 800 + 0,
-	.hsync_end = 800 + 1,
-	.htotal = 800 + 0 + 1 + 160,
-	.vdisplay = 480,
-	.vsync_start = 480 + 0,
-	.vsync_end = 480 + 48 + 1,
-	.vtotal = 480 + 48 + 1 + 0,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
-
-static const struct panel_desc mitsubishi_aa070mc01 = {
-	.modes = &mitsubishi_aa070mc01_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-
-	.delay = {
-		.enable = 200,
-		.unprepare = 200,
-		.disable = 400,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-};
-
-static const struct display_timing multi_inno_mi0700s4t_6_timing = {
-	.pixelclock = { 29000000, 33000000, 38000000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 180, 210, 240 },
-	.hback_porch = { 16, 16, 16 },
-	.hsync_len = { 30, 30, 30 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 12, 22, 32 },
-	.vback_porch = { 10, 10, 10 },
-	.vsync_len = { 13, 13, 13 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
-		 DISPLAY_FLAGS_SYNC_POSEDGE,
-};
-
-static const struct panel_desc multi_inno_mi0700s4t_6 = {
-	.timings = &multi_inno_mi0700s4t_6_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
-		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
-		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct display_timing multi_inno_mi0800ft_9_timing = {
-	.pixelclock = { 32000000, 40000000, 50000000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 16, 210, 354 },
-	.hback_porch = { 6, 26, 45 },
-	.hsync_len = { 1, 20, 40 },
-	.vactive = { 600, 600, 600 },
-	.vfront_porch = { 1, 12, 77 },
-	.vback_porch = { 3, 13, 22 },
-	.vsync_len = { 1, 10, 20 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
-		 DISPLAY_FLAGS_SYNC_POSEDGE,
-};
-
-static const struct panel_desc multi_inno_mi0800ft_9 = {
-	.timings = &multi_inno_mi0800ft_9_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 162,
-		.height = 122,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
-		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
-		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
-	.pixelclock = { 68900000, 70000000, 73400000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 30, 60, 71 },
-	.hback_porch = { 30, 60, 71 },
-	.hsync_len = { 10, 10, 48 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 5, 10, 10 },
-	.vback_porch = { 5, 10, 10 },
-	.vsync_len = { 5, 6, 13 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-		 DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc multi_inno_mi1010ait_1cp = {
-	.timings = &multi_inno_mi1010ait_1cp_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 217,
-		.height = 136,
-	},
-	.delay = {
-		.enable = 50,
-		.disable = 50,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing nec_nl12880bc20_05_timing = {
-	.pixelclock = { 67000000, 71000000, 75000000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 2, 30, 30 },
-	.hback_porch = { 6, 100, 100 },
-	.hsync_len = { 2, 30, 30 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 5, 5, 5 },
-	.vback_porch = { 11, 11, 11 },
-	.vsync_len = { 7, 7, 7 },
-};
-
-static const struct panel_desc nec_nl12880bc20_05 = {
-	.timings = &nec_nl12880bc20_05_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 261,
-		.height = 163,
-	},
-	.delay = {
-		.enable = 50,
-		.disable = 50,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
-	.clock = 10870,
-	.hdisplay = 480,
-	.hsync_start = 480 + 2,
-	.hsync_end = 480 + 2 + 41,
-	.htotal = 480 + 2 + 41 + 2,
-	.vdisplay = 272,
-	.vsync_start = 272 + 2,
-	.vsync_end = 272 + 2 + 4,
-	.vtotal = 272 + 2 + 4 + 2,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc nec_nl4827hc19_05b = {
-	.modes = &nec_nl4827hc19_05b_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 95,
-		.height = 54,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
-};
-
-static const struct drm_display_mode netron_dy_e231732_mode = {
-	.clock = 66000,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 160,
-	.hsync_end = 1024 + 160 + 70,
-	.htotal = 1024 + 160 + 70 + 90,
-	.vdisplay = 600,
-	.vsync_start = 600 + 127,
-	.vsync_end = 600 + 127 + 20,
-	.vtotal = 600 + 127 + 20 + 3,
-};
-
-static const struct panel_desc netron_dy_e231732 = {
-	.modes = &netron_dy_e231732_mode,
-	.num_modes = 1,
-	.size = {
-		.width = 154,
-		.height = 87,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-};
-
-static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 2,
-	.hsync_end = 480 + 2 + 41,
-	.htotal = 480 + 2 + 41 + 2,
-	.vdisplay = 272,
-	.vsync_start = 272 + 2,
-	.vsync_end = 272 + 2 + 10,
-	.vtotal = 272 + 2 + 10 + 2,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
-	.modes = &newhaven_nhd_43_480272ef_atxl_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 95,
-		.height = 54,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
-		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct display_timing nlt_nl192108ac18_02d_timing = {
-	.pixelclock = { 130000000, 148350000, 163000000 },
-	.hactive = { 1920, 1920, 1920 },
-	.hfront_porch = { 80, 100, 100 },
-	.hback_porch = { 100, 120, 120 },
-	.hsync_len = { 50, 60, 60 },
-	.vactive = { 1080, 1080, 1080 },
-	.vfront_porch = { 12, 30, 30 },
-	.vback_porch = { 4, 10, 10 },
-	.vsync_len = { 4, 5, 5 },
-};
-
-static const struct panel_desc nlt_nl192108ac18_02d = {
-	.timings = &nlt_nl192108ac18_02d_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 344,
-		.height = 194,
-	},
-	.delay = {
-		.unprepare = 500,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode nvd_9128_mode = {
-	.clock = 29500,
-	.hdisplay = 800,
-	.hsync_start = 800 + 130,
-	.hsync_end = 800 + 130 + 98,
-	.htotal = 800 + 0 + 130 + 98,
-	.vdisplay = 480,
-	.vsync_start = 480 + 10,
-	.vsync_end = 480 + 10 + 50,
-	.vtotal = 480 + 0 + 10 + 50,
-};
-
-static const struct panel_desc nvd_9128 = {
-	.modes = &nvd_9128_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 156,
-		.height = 88,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing okaya_rs800480t_7x0gp_timing = {
-	.pixelclock = { 30000000, 30000000, 40000000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 40, 40, 40 },
-	.hback_porch = { 40, 40, 40 },
-	.hsync_len = { 1, 48, 48 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 13, 13, 13 },
-	.vback_porch = { 29, 29, 29 },
-	.vsync_len = { 3, 3, 3 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc okaya_rs800480t_7x0gp = {
-	.timings = &okaya_rs800480t_7x0gp_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 154,
-		.height = 87,
-	},
-	.delay = {
-		.prepare = 41,
-		.enable = 50,
-		.unprepare = 41,
-		.disable = 50,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-};
-
-static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 5,
-	.hsync_end = 480 + 5 + 30,
-	.htotal = 480 + 5 + 30 + 10,
-	.vdisplay = 272,
-	.vsync_start = 272 + 8,
-	.vsync_end = 272 + 8 + 5,
-	.vtotal = 272 + 8 + 5 + 3,
-};
-
-static const struct panel_desc olimex_lcd_olinuxino_43ts = {
-	.modes = &olimex_lcd_olinuxino_43ts_mode,
-	.num_modes = 1,
-	.size = {
-		.width = 95,
-		.height = 54,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-};
-
-/*
- * 800x480 CVT. The panel appears to be quite accepting, at least as far as
- * pixel clocks, but this is the timing that was being used in the Adafruit
- * installation instructions.
- */
-static const struct drm_display_mode ontat_yx700wv03_mode = {
-	.clock = 29500,
-	.hdisplay = 800,
-	.hsync_start = 824,
-	.hsync_end = 896,
-	.htotal = 992,
-	.vdisplay = 480,
-	.vsync_start = 483,
-	.vsync_end = 493,
-	.vtotal = 500,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-/*
- * Specification at:
- * https://www.adafruit.com/images/product-files/2406/c3163.pdf
- */
-static const struct panel_desc ontat_yx700wv03 = {
-	.modes = &ontat_yx700wv03_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 154,
-		.height = 83,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-};
-
-static const struct drm_display_mode ortustech_com37h3m_mode  = {
-	.clock = 22230,
-	.hdisplay = 480,
-	.hsync_start = 480 + 40,
-	.hsync_end = 480 + 40 + 10,
-	.htotal = 480 + 40 + 10 + 40,
-	.vdisplay = 640,
-	.vsync_start = 640 + 4,
-	.vsync_end = 640 + 4 + 2,
-	.vtotal = 640 + 4 + 2 + 4,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc ortustech_com37h3m = {
-	.modes = &ortustech_com37h3m_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 56,	/* 56.16mm */
-		.height = 75,	/* 74.88mm */
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
-		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
-};
-
-static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
-	.clock = 25000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 10,
-	.hsync_end = 480 + 10 + 10,
-	.htotal = 480 + 10 + 10 + 15,
-	.vdisplay = 800,
-	.vsync_start = 800 + 3,
-	.vsync_end = 800 + 3 + 3,
-	.vtotal = 800 + 3 + 3 + 3,
-};
-
-static const struct panel_desc ortustech_com43h4m85ulc = {
-	.modes = &ortustech_com43h4m85ulc_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 56,
-		.height = 93,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode  = {
-	.clock = 33000,
-	.hdisplay = 800,
-	.hsync_start = 800 + 210,
-	.hsync_end = 800 + 210 + 30,
-	.htotal = 800 + 210 + 30 + 16,
-	.vdisplay = 480,
-	.vsync_start = 480 + 22,
-	.vsync_end = 480 + 22 + 13,
-	.vtotal = 480 + 22 + 13 + 10,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc osddisplays_osd070t1718_19ts = {
-	.modes = &osddisplays_osd070t1718_19ts_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
-		DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode pda_91_00156_a0_mode = {
-	.clock = 33300,
-	.hdisplay = 800,
-	.hsync_start = 800 + 1,
-	.hsync_end = 800 + 1 + 64,
-	.htotal = 800 + 1 + 64 + 64,
-	.vdisplay = 480,
-	.vsync_start = 480 + 1,
-	.vsync_end = 480 + 1 + 23,
-	.vtotal = 480 + 1 + 23 + 22,
-};
-
-static const struct panel_desc pda_91_00156_a0  = {
-	.modes = &pda_91_00156_a0_mode,
-	.num_modes = 1,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-};
-
-static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
-	.clock = 24750,
-	.hdisplay = 800,
-	.hsync_start = 800 + 54,
-	.hsync_end = 800 + 54 + 2,
-	.htotal = 800 + 54 + 2 + 44,
-	.vdisplay = 480,
-	.vsync_start = 480 + 49,
-	.vsync_end = 480 + 49 + 2,
-	.vtotal = 480 + 49 + 2 + 22,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc powertip_ph800480t013_idf02  = {
-	.modes = &powertip_ph800480t013_idf02_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
-		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
-		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode qd43003c0_40_mode = {
-	.clock = 9000,
-	.hdisplay = 480,
-	.hsync_start = 480 + 8,
-	.hsync_end = 480 + 8 + 4,
-	.htotal = 480 + 8 + 4 + 39,
-	.vdisplay = 272,
-	.vsync_start = 272 + 4,
-	.vsync_end = 272 + 4 + 10,
-	.vtotal = 272 + 4 + 10 + 2,
-};
-
-static const struct panel_desc qd43003c0_40 = {
-	.modes = &qd43003c0_40_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 95,
-		.height = 53,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-};
-
-static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
-	{ /* 60 Hz */
-		.clock = 10800,
-		.hdisplay = 480,
-		.hsync_start = 480 + 77,
-		.hsync_end = 480 + 77 + 41,
-		.htotal = 480 + 77 + 41 + 2,
-		.vdisplay = 272,
-		.vsync_start = 272 + 16,
-		.vsync_end = 272 + 16 + 10,
-		.vtotal = 272 + 16 + 10 + 2,
-		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-	},
-	{ /* 50 Hz */
-		.clock = 10800,
-		.hdisplay = 480,
-		.hsync_start = 480 + 17,
-		.hsync_end = 480 + 17 + 41,
-		.htotal = 480 + 17 + 41 + 2,
-		.vdisplay = 272,
-		.vsync_start = 272 + 116,
-		.vsync_end = 272 + 116 + 10,
-		.vtotal = 272 + 116 + 10 + 2,
-		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-	},
-};
-
-static const struct panel_desc qishenglong_gopher2b_lcd = {
-	.modes = qishenglong_gopher2b_lcd_modes,
-	.num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
-	.bpc = 8,
-	.size = {
-		.width = 95,
-		.height = 54,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct display_timing rocktech_rk043fn48h_timing = {
-	.pixelclock = { 6000000, 9000000, 12000000 },
-	.hactive = { 480, 480, 480 },
-	.hback_porch = { 8, 43, 43 },
-	.hfront_porch = { 2, 8, 8 },
-	.hsync_len = { 1, 1, 1 },
-	.vactive = { 272, 272, 272 },
-	.vback_porch = { 2, 12, 12 },
-	.vfront_porch = { 1, 4, 4 },
-	.vsync_len = { 1, 10, 10 },
-	.flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
-		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
-};
-
-static const struct panel_desc rocktech_rk043fn48h = {
-	.timings = &rocktech_rk043fn48h_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 95,
-		.height = 54,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct drm_display_mode raspberrypi_7inch_mode = {
-	.clock = 28569600 / 1000,
-	.hdisplay = 800,
-	.hsync_start = 800 + 48,
-	.hsync_end = 800 + 48 + 32,
-	.htotal = 800 + 48 + 32 + 80,
-	.vdisplay = 480,
-	.vsync_start = 480 + 3,
-	.vsync_end = 480 + 3 + 7,
-	.vtotal = 480 + 3 + 7 + 6,
-
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc raspberrypi_7inch = {
-	.modes = &raspberrypi_7inch_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.connector_type = DRM_MODE_CONNECTOR_DSI,
-};
-
-static const struct display_timing rocktech_rk070er9427_timing = {
-	.pixelclock = { 26400000, 33300000, 46800000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 16, 210, 354 },
-	.hback_porch = { 46, 46, 46 },
-	.hsync_len = { 1, 1, 1 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 7, 22, 147 },
-	.vback_porch = { 23, 23, 23 },
-	.vsync_len = { 1, 1, 1 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc rocktech_rk070er9427 = {
-	.timings = &rocktech_rk070er9427_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-	.delay = {
-		.prepare = 41,
-		.enable = 50,
-		.unprepare = 41,
-		.disable = 50,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-};
-
-static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
-	.clock = 71100,
-	.hdisplay = 1280,
-	.hsync_start = 1280 + 48,
-	.hsync_end = 1280 + 48 + 32,
-	.htotal = 1280 + 48 + 32 + 80,
-	.vdisplay = 800,
-	.vsync_start = 800 + 2,
-	.vsync_end = 800 + 2 + 5,
-	.vtotal = 800 + 2 + 5 + 16,
-};
-
-static const struct panel_desc rocktech_rk101ii01d_ct = {
-	.modes = &rocktech_rk101ii01d_ct_mode,
-	.bpc = 8,
-	.num_modes = 1,
-	.size = {
-		.width = 217,
-		.height = 136,
-	},
-	.delay = {
-		.prepare = 50,
-		.disable = 50,
-	},
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing samsung_ltl101al01_timing = {
-	.pixelclock = { 66663000, 66663000, 66663000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 18, 18, 18 },
-	.hback_porch = { 36, 36, 36 },
-	.hsync_len = { 16, 16, 16 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 4, 4, 4 },
-	.vback_porch = { 16, 16, 16 },
-	.vsync_len = { 3, 3, 3 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
-};
-
-static const struct panel_desc samsung_ltl101al01 = {
-	.timings = &samsung_ltl101al01_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 217,
-		.height = 135,
-	},
-	.delay = {
-		.prepare = 40,
-		.enable = 300,
-		.disable = 200,
-		.unprepare = 600,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode samsung_ltn101nt05_mode = {
-	.clock = 54030,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 24,
-	.hsync_end = 1024 + 24 + 136,
-	.htotal = 1024 + 24 + 136 + 160,
-	.vdisplay = 600,
-	.vsync_start = 600 + 3,
-	.vsync_end = 600 + 3 + 6,
-	.vtotal = 600 + 3 + 6 + 61,
-};
-
-static const struct panel_desc samsung_ltn101nt05 = {
-	.modes = &samsung_ltn101nt05_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 223,
-		.height = 125,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct display_timing satoz_sat050at40h12r2_timing = {
-	.pixelclock = {33300000, 33300000, 50000000},
-	.hactive = {800, 800, 800},
-	.hfront_porch = {16, 210, 354},
-	.hback_porch = {46, 46, 46},
-	.hsync_len = {1, 1, 40},
-	.vactive = {480, 480, 480},
-	.vfront_porch = {7, 22, 147},
-	.vback_porch = {23, 23, 23},
-	.vsync_len = {1, 1, 20},
-};
-
-static const struct panel_desc satoz_sat050at40h12r2 = {
-	.timings = &satoz_sat050at40h12r2_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 108,
-		.height = 65,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
-	.clock = 33260,
-	.hdisplay = 800,
-	.hsync_start = 800 + 64,
-	.hsync_end = 800 + 64 + 128,
-	.htotal = 800 + 64 + 128 + 64,
-	.vdisplay = 480,
-	.vsync_start = 480 + 8,
-	.vsync_end = 480 + 8 + 2,
-	.vtotal = 480 + 8 + 2 + 35,
-	.flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
-};
-
-static const struct panel_desc sharp_lq070y3dg3b = {
-	.modes = &sharp_lq070y3dg3b_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 152,	/* 152.4mm */
-		.height = 91,	/* 91.4mm */
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
-		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
-};
-
-static const struct drm_display_mode sharp_lq035q7db03_mode = {
-	.clock = 5500,
-	.hdisplay = 240,
-	.hsync_start = 240 + 16,
-	.hsync_end = 240 + 16 + 7,
-	.htotal = 240 + 16 + 7 + 5,
-	.vdisplay = 320,
-	.vsync_start = 320 + 9,
-	.vsync_end = 320 + 9 + 1,
-	.vtotal = 320 + 9 + 1 + 7,
-};
-
-static const struct panel_desc sharp_lq035q7db03 = {
-	.modes = &sharp_lq035q7db03_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 54,
-		.height = 72,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-};
-
-static const struct display_timing sharp_lq101k1ly04_timing = {
-	.pixelclock = { 60000000, 65000000, 80000000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 20, 20, 20 },
-	.hback_porch = { 20, 20, 20 },
-	.hsync_len = { 10, 10, 10 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 4, 4, 4 },
-	.vback_porch = { 4, 4, 4 },
-	.vsync_len = { 4, 4, 4 },
-	.flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
-};
-
-static const struct panel_desc sharp_lq101k1ly04 = {
-	.timings = &sharp_lq101k1ly04_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 217,
-		.height = 136,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
-	{ /* 50 Hz */
-		.clock = 3000,
-		.hdisplay = 240,
-		.hsync_start = 240 + 58,
-		.hsync_end = 240 + 58 + 1,
-		.htotal = 240 + 58 + 1 + 1,
-		.vdisplay = 160,
-		.vsync_start = 160 + 24,
-		.vsync_end = 160 + 24 + 10,
-		.vtotal = 160 + 24 + 10 + 6,
-		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
-	},
-	{ /* 60 Hz */
-		.clock = 3000,
-		.hdisplay = 240,
-		.hsync_start = 240 + 8,
-		.hsync_end = 240 + 8 + 1,
-		.htotal = 240 + 8 + 1 + 1,
-		.vdisplay = 160,
-		.vsync_start = 160 + 24,
-		.vsync_end = 160 + 24 + 10,
-		.vtotal = 160 + 24 + 10 + 6,
-		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
-	},
-};
-
-static const struct panel_desc sharp_ls020b1dd01d = {
-	.modes = sharp_ls020b1dd01d_modes,
-	.num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
-	.bpc = 6,
-	.size = {
-		.width = 42,
-		.height = 28,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH
-		   | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
-		   | DRM_BUS_FLAG_SHARP_SIGNALS,
-};
-
-static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
-	.clock = 33300,
-	.hdisplay = 800,
-	.hsync_start = 800 + 1,
-	.hsync_end = 800 + 1 + 64,
-	.htotal = 800 + 1 + 64 + 64,
-	.vdisplay = 480,
-	.vsync_start = 480 + 1,
-	.vsync_end = 480 + 1 + 23,
-	.vtotal = 480 + 1 + 23 + 22,
-};
-
-static const struct panel_desc shelly_sca07010_bfn_lnn = {
-	.modes = &shelly_sca07010_bfn_lnn_mode,
-	.num_modes = 1,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-};
-
-static const struct drm_display_mode starry_kr070pe2t_mode = {
-	.clock = 33000,
-	.hdisplay = 800,
-	.hsync_start = 800 + 209,
-	.hsync_end = 800 + 209 + 1,
-	.htotal = 800 + 209 + 1 + 45,
-	.vdisplay = 480,
-	.vsync_start = 480 + 22,
-	.vsync_end = 480 + 22 + 1,
-	.vtotal = 480 + 22 + 1 + 22,
-};
-
-static const struct panel_desc starry_kr070pe2t = {
-	.modes = &starry_kr070pe2t_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 152,
-		.height = 86,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-};
-
-static const struct display_timing startek_kd070wvfpa_mode = {
-	.pixelclock = { 25200000, 27200000, 30500000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 19, 44, 115 },
-	.hback_porch = { 5, 16, 101 },
-	.hsync_len = { 1, 2, 100 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 5, 43, 67 },
-	.vback_porch = { 5, 5, 67 },
-	.vsync_len = { 1, 2, 66 },
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
-		 DISPLAY_FLAGS_SYNC_POSEDGE,
-};
-
-static const struct panel_desc startek_kd070wvfpa = {
-	.timings = &startek_kd070wvfpa_mode,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.delay = {
-		.prepare = 20,
-		.enable = 200,
-		.disable = 200,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.connector_type = DRM_MODE_CONNECTOR_DPI,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
-		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
-		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
-};
-
-static const struct display_timing tsd_tst043015cmhx_timing = {
-	.pixelclock = { 5000000, 9000000, 12000000 },
-	.hactive = { 480, 480, 480 },
-	.hfront_porch = { 4, 5, 65 },
-	.hback_porch = { 36, 40, 255 },
-	.hsync_len = { 1, 1, 1 },
-	.vactive = { 272, 272, 272 },
-	.vfront_porch = { 2, 8, 97 },
-	.vback_porch = { 3, 8, 31 },
-	.vsync_len = { 1, 1, 1 },
-
-	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
-};
-
-static const struct panel_desc tsd_tst043015cmhx = {
-	.timings = &tsd_tst043015cmhx_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 105,
-		.height = 67,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
-};
-
-static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
-	.clock = 30000,
-	.hdisplay = 800,
-	.hsync_start = 800 + 39,
-	.hsync_end = 800 + 39 + 47,
-	.htotal = 800 + 39 + 47 + 39,
-	.vdisplay = 480,
-	.vsync_start = 480 + 13,
-	.vsync_end = 480 + 13 + 2,
-	.vtotal = 480 + 13 + 2 + 29,
-};
-
-static const struct panel_desc tfc_s9700rtwv43tr_01b = {
-	.modes = &tfc_s9700rtwv43tr_01b_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 155,
-		.height = 90,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
-};
-
-static const struct display_timing tianma_tm070jdhg30_timing = {
-	.pixelclock = { 62600000, 68200000, 78100000 },
-	.hactive = { 1280, 1280, 1280 },
-	.hfront_porch = { 15, 64, 159 },
-	.hback_porch = { 5, 5, 5 },
-	.hsync_len = { 1, 1, 256 },
-	.vactive = { 800, 800, 800 },
-	.vfront_porch = { 3, 40, 99 },
-	.vback_porch = { 2, 2, 2 },
-	.vsync_len = { 1, 1, 128 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc tianma_tm070jdhg30 = {
-	.timings = &tianma_tm070jdhg30_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 151,
-		.height = 95,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-};
-
-static const struct panel_desc tianma_tm070jvhg33 = {
-	.timings = &tianma_tm070jdhg30_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 150,
-		.height = 94,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-};
-
-static const struct display_timing tianma_tm070rvhg71_timing = {
-	.pixelclock = { 27700000, 29200000, 39600000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 12, 40, 212 },
-	.hback_porch = { 88, 88, 88 },
-	.hsync_len = { 1, 1, 40 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 1, 13, 88 },
-	.vback_porch = { 32, 32, 32 },
-	.vsync_len = { 1, 1, 3 },
-	.flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-static const struct panel_desc tianma_tm070rvhg71 = {
-	.timings = &tianma_tm070rvhg71_timing,
-	.num_timings = 1,
-	.bpc = 8,
-	.size = {
-		.width = 154,
-		.height = 86,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
-	{
-		.clock = 10000,
-		.hdisplay = 320,
-		.hsync_start = 320 + 50,
-		.hsync_end = 320 + 50 + 6,
-		.htotal = 320 + 50 + 6 + 38,
-		.vdisplay = 240,
-		.vsync_start = 240 + 3,
-		.vsync_end = 240 + 3 + 1,
-		.vtotal = 240 + 3 + 1 + 17,
-		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-	},
-};
-
-static const struct panel_desc ti_nspire_cx_lcd_panel = {
-	.modes = ti_nspire_cx_lcd_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 65,
-		.height = 49,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
-};
-
-static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
-	{
-		.clock = 10000,
-		.hdisplay = 320,
-		.hsync_start = 320 + 6,
-		.hsync_end = 320 + 6 + 6,
-		.htotal = 320 + 6 + 6 + 6,
-		.vdisplay = 240,
-		.vsync_start = 240 + 0,
-		.vsync_end = 240 + 0 + 1,
-		.vtotal = 240 + 0 + 1 + 0,
-		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
-	},
-};
-
-static const struct panel_desc ti_nspire_classic_lcd_panel = {
-	.modes = ti_nspire_classic_lcd_mode,
-	.num_modes = 1,
-	/* The grayscale panel has 8 bit for the color .. Y (black) */
-	.bpc = 8,
-	.size = {
-		.width = 71,
-		.height = 53,
-	},
-	/* This is the grayscale bus format */
-	.bus_format = MEDIA_BUS_FMT_Y8_1X8,
-	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
-};
-
-static const struct drm_display_mode toshiba_lt089ac29000_mode = {
-	.clock = 79500,
-	.hdisplay = 1280,
-	.hsync_start = 1280 + 192,
-	.hsync_end = 1280 + 192 + 128,
-	.htotal = 1280 + 192 + 128 + 64,
-	.vdisplay = 768,
-	.vsync_start = 768 + 20,
-	.vsync_end = 768 + 20 + 7,
-	.vtotal = 768 + 20 + 7 + 3,
-};
-
-static const struct panel_desc toshiba_lt089ac29000 = {
-	.modes = &toshiba_lt089ac29000_mode,
-	.num_modes = 1,
-	.size = {
-		.width = 194,
-		.height = 116,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode tpk_f07a_0102_mode = {
-	.clock = 33260,
-	.hdisplay = 800,
-	.hsync_start = 800 + 40,
-	.hsync_end = 800 + 40 + 128,
-	.htotal = 800 + 40 + 128 + 88,
-	.vdisplay = 480,
-	.vsync_start = 480 + 10,
-	.vsync_end = 480 + 10 + 2,
-	.vtotal = 480 + 10 + 2 + 33,
-};
-
-static const struct panel_desc tpk_f07a_0102 = {
-	.modes = &tpk_f07a_0102_mode,
-	.num_modes = 1,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
-};
-
-static const struct drm_display_mode tpk_f10a_0102_mode = {
-	.clock = 45000,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 176,
-	.hsync_end = 1024 + 176 + 5,
-	.htotal = 1024 + 176 + 5 + 88,
-	.vdisplay = 600,
-	.vsync_start = 600 + 20,
-	.vsync_end = 600 + 20 + 5,
-	.vtotal = 600 + 20 + 5 + 25,
-};
-
-static const struct panel_desc tpk_f10a_0102 = {
-	.modes = &tpk_f10a_0102_mode,
-	.num_modes = 1,
-	.size = {
-		.width = 223,
-		.height = 125,
-	},
-};
-
-static const struct display_timing urt_umsh_8596md_timing = {
-	.pixelclock = { 33260000, 33260000, 33260000 },
-	.hactive = { 800, 800, 800 },
-	.hfront_porch = { 41, 41, 41 },
-	.hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
-	.hsync_len = { 71, 128, 128 },
-	.vactive = { 480, 480, 480 },
-	.vfront_porch = { 10, 10, 10 },
-	.vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
-	.vsync_len = { 2, 2, 2 },
-	.flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
-		DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
-};
-
-static const struct panel_desc urt_umsh_8596md_lvds = {
-	.timings = &urt_umsh_8596md_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct panel_desc urt_umsh_8596md_parallel = {
-	.timings = &urt_umsh_8596md_timing,
-	.num_timings = 1,
-	.bpc = 6,
-	.size = {
-		.width = 152,
-		.height = 91,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
-};
-
-static const struct drm_display_mode vivax_tpc9150_panel_mode = {
-	.clock = 60000,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 160,
-	.hsync_end = 1024 + 160 + 100,
-	.htotal = 1024 + 160 + 100 + 60,
-	.vdisplay = 600,
-	.vsync_start = 600 + 12,
-	.vsync_end = 600 + 12 + 10,
-	.vtotal = 600 + 12 + 10 + 13,
-};
-
-static const struct panel_desc vivax_tpc9150_panel = {
-	.modes = &vivax_tpc9150_panel_mode,
-	.num_modes = 1,
-	.bpc = 6,
-	.size = {
-		.width = 200,
-		.height = 115,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode vl050_8048nt_c01_mode = {
-	.clock = 33333,
-	.hdisplay = 800,
-	.hsync_start = 800 + 210,
-	.hsync_end = 800 + 210 + 20,
-	.htotal = 800 + 210 + 20 + 46,
-	.vdisplay =  480,
-	.vsync_start = 480 + 22,
-	.vsync_end = 480 + 22 + 10,
-	.vtotal = 480 + 22 + 10 + 23,
-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
-};
-
-static const struct panel_desc vl050_8048nt_c01 = {
-	.modes = &vl050_8048nt_c01_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 120,
-		.height = 76,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
-};
-
-static const struct drm_display_mode winstar_wf35ltiacd_mode = {
-	.clock = 6410,
-	.hdisplay = 320,
-	.hsync_start = 320 + 20,
-	.hsync_end = 320 + 20 + 30,
-	.htotal = 320 + 20 + 30 + 38,
-	.vdisplay = 240,
-	.vsync_start = 240 + 4,
-	.vsync_end = 240 + 4 + 3,
-	.vtotal = 240 + 4 + 3 + 15,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
-static const struct panel_desc winstar_wf35ltiacd = {
-	.modes = &winstar_wf35ltiacd_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 70,
-		.height = 53,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-};
-
-static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
-	.clock = 51200,
-	.hdisplay = 1024,
-	.hsync_start = 1024 + 100,
-	.hsync_end = 1024 + 100 + 100,
-	.htotal = 1024 + 100 + 100 + 120,
-	.vdisplay = 600,
-	.vsync_start = 600 + 10,
-	.vsync_end = 600 + 10 + 10,
-	.vtotal = 600 + 10 + 10 + 15,
-	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
-};
-
-static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
-	.modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 154,
-		.height = 90,
-	},
-	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
-	.connector_type = DRM_MODE_CONNECTOR_LVDS,
-};
-
-static const struct drm_display_mode arm_rtsm_mode[] = {
-	{
-		.clock = 65000,
-		.hdisplay = 1024,
-		.hsync_start = 1024 + 24,
-		.hsync_end = 1024 + 24 + 136,
-		.htotal = 1024 + 24 + 136 + 160,
-		.vdisplay = 768,
-		.vsync_start = 768 + 3,
-		.vsync_end = 768 + 3 + 6,
-		.vtotal = 768 + 3 + 6 + 29,
-		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-	},
-};
-
-static const struct panel_desc arm_rtsm = {
-	.modes = arm_rtsm_mode,
-	.num_modes = 1,
-	.bpc = 8,
-	.size = {
-		.width = 400,
-		.height = 300,
-	},
-	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+	.connector_type = DRM_MODE_CONNECTOR_DSI,
 };
 
 static const struct of_device_id platform_of_match[] = {
 	{
-		.compatible = "ampire,am-1280800n3tzqw-t00h",
-		.data = &ampire_am_1280800n3tzqw_t00h,
-	}, {
-		.compatible = "ampire,am-480272h3tmqw-t01h",
-		.data = &ampire_am_480272h3tmqw_t01h,
-	}, {
-		.compatible = "ampire,am-800480l1tmqw-t00h",
-		.data = &ampire_am_800480l1tmqw_t00h,
-	}, {
-		.compatible = "ampire,am800480r3tmqwa1h",
-		.data = &ampire_am800480r3tmqwa1h,
-	}, {
-		.compatible = "ampire,am800600p5tmqw-tb8h",
-		.data = &ampire_am800600p5tmqwtb8h,
-	}, {
-		.compatible = "arm,rtsm-display",
-		.data = &arm_rtsm,
-	}, {
-		.compatible = "armadeus,st0700-adapt",
-		.data = &armadeus_st0700_adapt,
-	}, {
-		.compatible = "auo,b101aw03",
-		.data = &auo_b101aw03,
-	}, {
-		.compatible = "auo,b101xtn01",
-		.data = &auo_b101xtn01,
-	}, {
-		.compatible = "auo,b116xw03",
-		.data = &auo_b116xw03,
-	}, {
-		.compatible = "auo,g070vvn01",
-		.data = &auo_g070vvn01,
-	}, {
-		.compatible = "auo,g101evn010",
-		.data = &auo_g101evn010,
-	}, {
-		.compatible = "auo,g104sn02",
-		.data = &auo_g104sn02,
-	}, {
-		.compatible = "auo,g121ean01",
-		.data = &auo_g121ean01,
-	}, {
-		.compatible = "auo,g133han01",
-		.data = &auo_g133han01,
-	}, {
-		.compatible = "auo,g156xtn01",
-		.data = &auo_g156xtn01,
-	}, {
-		.compatible = "auo,g185han01",
-		.data = &auo_g185han01,
-	}, {
-		.compatible = "auo,g190ean01",
-		.data = &auo_g190ean01,
-	}, {
-		.compatible = "auo,p320hvn03",
-		.data = &auo_p320hvn03,
-	}, {
-		.compatible = "auo,t215hvn01",
-		.data = &auo_t215hvn01,
-	}, {
-		.compatible = "avic,tm070ddh03",
-		.data = &avic_tm070ddh03,
-	}, {
-		.compatible = "bananapi,s070wv20-ct16",
-		.data = &bananapi_s070wv20_ct16,
-	}, {
-		.compatible = "boe,ev121wxm-n10-1850",
-		.data = &boe_ev121wxm_n10_1850,
-	}, {
-		.compatible = "boe,hv070wsa-100",
-		.data = &boe_hv070wsa
-	}, {
-		.compatible = "cdtech,s043wq26h-ct7",
-		.data = &cdtech_s043wq26h_ct7,
-	}, {
-		.compatible = "cdtech,s070pws19hp-fc21",
-		.data = &cdtech_s070pws19hp_fc21,
-	}, {
-		.compatible = "cdtech,s070swv29hg-dc44",
-		.data = &cdtech_s070swv29hg_dc44,
-	}, {
-		.compatible = "cdtech,s070wv95-ct16",
-		.data = &cdtech_s070wv95_ct16,
-	}, {
-		.compatible = "chefree,ch101olhlwh-002",
-		.data = &chefree_ch101olhlwh_002,
-	}, {
-		.compatible = "chunghwa,claa070wp03xg",
-		.data = &chunghwa_claa070wp03xg,
-	}, {
-		.compatible = "chunghwa,claa101wa01a",
-		.data = &chunghwa_claa101wa01a
-	}, {
-		.compatible = "chunghwa,claa101wb01",
-		.data = &chunghwa_claa101wb01
-	}, {
-		.compatible = "dataimage,fg040346dsswbg04",
-		.data = &dataimage_fg040346dsswbg04,
-	}, {
-		.compatible = "dataimage,fg1001l0dsswmg01",
-		.data = &dataimage_fg1001l0dsswmg01,
-	}, {
-		.compatible = "dataimage,scf0700c48ggu18",
-		.data = &dataimage_scf0700c48ggu18,
-	}, {
-		.compatible = "dlc,dlc0700yzg-1",
-		.data = &dlc_dlc0700yzg_1,
-	}, {
-		.compatible = "dlc,dlc1010gig",
-		.data = &dlc_dlc1010gig,
-	}, {
-		.compatible = "edt,et035012dm6",
-		.data = &edt_et035012dm6,
-	}, {
-		.compatible = "edt,etm0350g0dh6",
-		.data = &edt_etm0350g0dh6,
-	}, {
-		.compatible = "edt,etm043080dh6gp",
-		.data = &edt_etm043080dh6gp,
-	}, {
-		.compatible = "edt,etm0430g0dh6",
-		.data = &edt_etm0430g0dh6,
-	}, {
-		.compatible = "edt,et057090dhu",
-		.data = &edt_et057090dhu,
-	}, {
-		.compatible = "edt,et070080dh6",
-		.data = &edt_etm0700g0dh6,
-	}, {
-		.compatible = "edt,etm0700g0dh6",
-		.data = &edt_etm0700g0dh6,
-	}, {
-		.compatible = "edt,etm0700g0bdh6",
-		.data = &edt_etm0700g0bdh6,
-	}, {
-		.compatible = "edt,etm0700g0edh6",
-		.data = &edt_etm0700g0bdh6,
-	}, {
-		.compatible = "edt,etml0700y5dha",
-		.data = &edt_etml0700y5dha,
-	}, {
-		.compatible = "edt,etmv570g2dhu",
-		.data = &edt_etmv570g2dhu,
-	}, {
-		.compatible = "eink,vb3300-kca",
-		.data = &eink_vb3300_kca,
-	}, {
-		.compatible = "evervision,vgg804821",
-		.data = &evervision_vgg804821,
-	}, {
-		.compatible = "foxlink,fl500wvr00-a0t",
-		.data = &foxlink_fl500wvr00_a0t,
-	}, {
-		.compatible = "frida,frd350h54004",
-		.data = &frida_frd350h54004,
-	}, {
-		.compatible = "friendlyarm,hd702e",
-		.data = &friendlyarm_hd702e,
-	}, {
-		.compatible = "giantplus,gpg482739qs5",
-		.data = &giantplus_gpg482739qs5
-	}, {
-		.compatible = "giantplus,gpm940b0",
-		.data = &giantplus_gpm940b0,
-	}, {
-		.compatible = "hannstar,hsd070pww1",
-		.data = &hannstar_hsd070pww1,
-	}, {
-		.compatible = "hannstar,hsd100pxn1",
-		.data = &hannstar_hsd100pxn1,
-	}, {
-		.compatible = "hannstar,hsd101pww2",
-		.data = &hannstar_hsd101pww2,
-	}, {
-		.compatible = "hit,tx23d38vm0caa",
-		.data = &hitachi_tx23d38vm0caa
-	}, {
-		.compatible = "innolux,at043tn24",
-		.data = &innolux_at043tn24,
-	}, {
-		.compatible = "innolux,at070tn92",
-		.data = &innolux_at070tn92,
-	}, {
-		.compatible = "innolux,g070ace-l01",
-		.data = &innolux_g070ace_l01,
-	}, {
-		.compatible = "innolux,g070y2-l01",
-		.data = &innolux_g070y2_l01,
-	}, {
-		.compatible = "innolux,g070y2-t02",
-		.data = &innolux_g070y2_t02,
-	}, {
-		.compatible = "innolux,g101ice-l01",
-		.data = &innolux_g101ice_l01
-	}, {
-		.compatible = "innolux,g121i1-l01",
-		.data = &innolux_g121i1_l01
-	}, {
-		.compatible = "innolux,g121x1-l03",
-		.data = &innolux_g121x1_l03,
-	}, {
-		.compatible = "innolux,g156hce-l01",
-		.data = &innolux_g156hce_l01,
-	}, {
-		.compatible = "innolux,n156bge-l21",
-		.data = &innolux_n156bge_l21,
-	}, {
-		.compatible = "innolux,zj070na-01p",
-		.data = &innolux_zj070na_01p,
-	}, {
-		.compatible = "koe,tx14d24vm1bpa",
-		.data = &koe_tx14d24vm1bpa,
-	}, {
-		.compatible = "koe,tx26d202vm0bwa",
-		.data = &koe_tx26d202vm0bwa,
-	}, {
-		.compatible = "koe,tx31d200vm0baa",
-		.data = &koe_tx31d200vm0baa,
-	}, {
-		.compatible = "kyo,tcg121xglp",
-		.data = &kyo_tcg121xglp,
-	}, {
-		.compatible = "lemaker,bl035-rgb-002",
-		.data = &lemaker_bl035_rgb_002,
-	}, {
-		.compatible = "lg,lb070wv8",
-		.data = &lg_lb070wv8,
-	}, {
-		.compatible = "lincolntech,lcd185-101ct",
-		.data = &lincolntech_lcd185_101ct,
-	}, {
-		.compatible = "logicpd,type28",
-		.data = &logicpd_type_28,
-	}, {
-		.compatible = "logictechno,lt161010-2nhc",
-		.data = &logictechno_lt161010_2nh,
-	}, {
-		.compatible = "logictechno,lt161010-2nhr",
-		.data = &logictechno_lt161010_2nh,
-	}, {
-		.compatible = "logictechno,lt170410-2whc",
-		.data = &logictechno_lt170410_2whc,
-	}, {
-		.compatible = "logictechno,lttd800480070-l2rt",
-		.data = &logictechno_lttd800480070_l2rt,
-	}, {
-		.compatible = "logictechno,lttd800480070-l6wh-rt",
-		.data = &logictechno_lttd800480070_l6wh_rt,
-	}, {
-		.compatible = "microtips,mf-101hiebcaf0",
-		.data = &microtips_mf_101hiebcaf0_c,
-	}, {
-		.compatible = "microtips,mf-103hieb0ga0",
-		.data = &microtips_mf_103hieb0ga0,
-	}, {
-		.compatible = "mitsubishi,aa070mc01-ca1",
-		.data = &mitsubishi_aa070mc01,
-	}, {
-		.compatible = "multi-inno,mi0700s4t-6",
-		.data = &multi_inno_mi0700s4t_6,
-	}, {
-		.compatible = "multi-inno,mi0800ft-9",
-		.data = &multi_inno_mi0800ft_9,
-	}, {
-		.compatible = "multi-inno,mi1010ait-1cp",
-		.data = &multi_inno_mi1010ait_1cp,
-	}, {
-		.compatible = "nec,nl12880bc20-05",
-		.data = &nec_nl12880bc20_05,
-	}, {
-		.compatible = "nec,nl4827hc19-05b",
-		.data = &nec_nl4827hc19_05b,
-	}, {
-		.compatible = "netron-dy,e231732",
-		.data = &netron_dy_e231732,
-	}, {
-		.compatible = "newhaven,nhd-4.3-480272ef-atxl",
-		.data = &newhaven_nhd_43_480272ef_atxl,
-	}, {
-		.compatible = "nlt,nl192108ac18-02d",
-		.data = &nlt_nl192108ac18_02d,
-	}, {
-		.compatible = "nvd,9128",
-		.data = &nvd_9128,
-	}, {
-		.compatible = "okaya,rs800480t-7x0gp",
-		.data = &okaya_rs800480t_7x0gp,
-	}, {
-		.compatible = "olimex,lcd-olinuxino-43-ts",
-		.data = &olimex_lcd_olinuxino_43ts,
-	}, {
-		.compatible = "ontat,yx700wv03",
-		.data = &ontat_yx700wv03,
-	}, {
-		.compatible = "ortustech,com37h3m05dtc",
-		.data = &ortustech_com37h3m,
-	}, {
-		.compatible = "ortustech,com37h3m99dtc",
-		.data = &ortustech_com37h3m,
-	}, {
-		.compatible = "ortustech,com43h4m85ulc",
-		.data = &ortustech_com43h4m85ulc,
-	}, {
-		.compatible = "osddisplays,osd070t1718-19ts",
-		.data = &osddisplays_osd070t1718_19ts,
-	}, {
-		.compatible = "pda,91-00156-a0",
-		.data = &pda_91_00156_a0,
-	}, {
-		.compatible = "powertip,ph800480t013-idf02",
-		.data = &powertip_ph800480t013_idf02,
-	}, {
-		.compatible = "qiaodian,qd43003c0-40",
-		.data = &qd43003c0_40,
-	}, {
-		.compatible = "qishenglong,gopher2b-lcd",
-		.data = &qishenglong_gopher2b_lcd,
-	}, {
-		.compatible = "rocktech,rk043fn48h",
-		.data = &rocktech_rk043fn48h,
-	}, {
 		.compatible = "raspberrypi,7inch-dsi",
 		.data = &raspberrypi_7inch,
 	}, {
-		.compatible = "rocktech,rk070er9427",
-		.data = &rocktech_rk070er9427,
-	}, {
-		.compatible = "rocktech,rk101ii01d-ct",
-		.data = &rocktech_rk101ii01d_ct,
-	}, {
-		.compatible = "samsung,ltl101al01",
-		.data = &samsung_ltl101al01,
-	}, {
-		.compatible = "samsung,ltn101nt05",
-		.data = &samsung_ltn101nt05,
-	}, {
-		.compatible = "satoz,sat050at40h12r2",
-		.data = &satoz_sat050at40h12r2,
-	}, {
-		.compatible = "sharp,lq035q7db03",
-		.data = &sharp_lq035q7db03,
-	}, {
-		.compatible = "sharp,lq070y3dg3b",
-		.data = &sharp_lq070y3dg3b,
-	}, {
-		.compatible = "sharp,lq101k1ly04",
-		.data = &sharp_lq101k1ly04,
-	}, {
-		.compatible = "sharp,ls020b1dd01d",
-		.data = &sharp_ls020b1dd01d,
-	}, {
-		.compatible = "shelly,sca07010-bfn-lnn",
-		.data = &shelly_sca07010_bfn_lnn,
-	}, {
-		.compatible = "starry,kr070pe2t",
-		.data = &starry_kr070pe2t,
-	}, {
-		.compatible = "startek,kd070wvfpa",
-		.data = &startek_kd070wvfpa,
-	}, {
-		.compatible = "team-source-display,tst043015cmhx",
-		.data = &tsd_tst043015cmhx,
-	}, {
-		.compatible = "tfc,s9700rtwv43tr-01b",
-		.data = &tfc_s9700rtwv43tr_01b,
-	}, {
-		.compatible = "tianma,tm070jdhg30",
-		.data = &tianma_tm070jdhg30,
-	}, {
-		.compatible = "tianma,tm070jvhg33",
-		.data = &tianma_tm070jvhg33,
-	}, {
-		.compatible = "tianma,tm070rvhg71",
-		.data = &tianma_tm070rvhg71,
-	}, {
-		.compatible = "ti,nspire-cx-lcd-panel",
-		.data = &ti_nspire_cx_lcd_panel,
-	}, {
-		.compatible = "ti,nspire-classic-lcd-panel",
-		.data = &ti_nspire_classic_lcd_panel,
-	}, {
-		.compatible = "toshiba,lt089ac29000",
-		.data = &toshiba_lt089ac29000,
-	}, {
-		.compatible = "tpk,f07a-0102",
-		.data = &tpk_f07a_0102,
-	}, {
-		.compatible = "tpk,f10a-0102",
-		.data = &tpk_f10a_0102,
-	}, {
-		.compatible = "urt,umsh-8596md-t",
-		.data = &urt_umsh_8596md_parallel,
-	}, {
-		.compatible = "urt,umsh-8596md-1t",
-		.data = &urt_umsh_8596md_parallel,
-	}, {
-		.compatible = "urt,umsh-8596md-7t",
-		.data = &urt_umsh_8596md_parallel,
-	}, {
-		.compatible = "urt,umsh-8596md-11t",
-		.data = &urt_umsh_8596md_lvds,
-	}, {
-		.compatible = "urt,umsh-8596md-19t",
-		.data = &urt_umsh_8596md_lvds,
-	}, {
-		.compatible = "urt,umsh-8596md-20t",
-		.data = &urt_umsh_8596md_parallel,
-	}, {
-		.compatible = "vivax,tpc9150-panel",
-		.data = &vivax_tpc9150_panel,
-	}, {
-		.compatible = "vxt,vl050-8048nt-c01",
-		.data = &vl050_8048nt_c01,
-	}, {
-		.compatible = "winstar,wf35ltiacd",
-		.data = &winstar_wf35ltiacd,
-	}, {
-		.compatible = "yes-optoelectronics,ytc700tlag-05-201c",
-		.data = &yes_optoelectronics_ytc700tlag_05_201c,
+		.compatible = "dummy,bt656_PAL",
+		.data = &bt656_PAL,
 	}, {
 		/* Must be the last entry */
 		.compatible = "panel-dpi",
diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c
index 14691f346..fc3003a05 100644
--- a/drivers/gpu/drm/tidss/tidss_crtc.c
+++ b/drivers/gpu/drm/tidss/tidss_crtc.c
@@ -114,7 +114,8 @@ static int tidss_crtc_atomic_check(struct drm_crtc *crtc,
 		return -EINVAL;
 	}
 
-	drm_mode_set_crtcinfo(&crtc_state->adjusted_mode, 0);
+	//drm_mode_set_crtcinfo(&crtc_state->adjusted_mode, 0);
+	drm_mode_set_crtcinfo(&crtc_state->adjusted_mode, mode->flags & DRM_MODE_FLAG_INTERLACE ? CRTC_INTERLACE_HALVE_V : 0);
 	return dispc_vp_bus_check(dispc, hw_videoport, crtc_state);
 }
 
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index 60f69be36..2a88203d8 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -26,6 +26,7 @@
 #include <drm/drm_framebuffer.h>
 #include <drm/drm_gem_dma_helper.h>
 #include <drm/drm_panel.h>
+#include <drm/drm_atomic.h>
 
 #include "tidss_crtc.h"
 #include "tidss_dispc.h"
@@ -36,6 +37,9 @@
 #include "tidss_dispc_regs.h"
 #include "tidss_scale_coefs.h"
 
+#define MSG(fmt, args...) printk(KERN_ERR "\033[32m<dispc> "fmt" %s", ##args,"")
+
+
 static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
 	[DSS_REVISION_OFF] =                    0x00,
 	[DSS_SYSCONFIG_OFF] =                   0x04,
@@ -820,7 +824,7 @@ void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
 {
 	dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc);
 
-	/* clear the irqstatus for newly enabled irqs */
+	/* clear the irqstatus for irqs that will be enabled */
 	dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask);
 
 	dispc_k2g_vp_set_irqenable(dispc, 0, mask);
@@ -828,6 +832,9 @@ void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
 
 	dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7));
 
+	/* clear the irqstatus for irqs that were disabled */
+	dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & old_mask);
+
 	/* flush posted write */
 	dispc_k2g_read_irqenable(dispc);
 }
@@ -900,24 +907,17 @@ static
 void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask)
 {
 	unsigned int i;
-	u32 top_clear = 0;
 
 	for (i = 0; i < dispc->feat->num_vps; ++i) {
-		if (clearmask & DSS_IRQ_VP_MASK(i)) {
+		if (clearmask & DSS_IRQ_VP_MASK(i)) 
 			dispc_k3_vp_write_irqstatus(dispc, i, clearmask);
-			top_clear |= BIT(i);
-		}
 	}
 	for (i = 0; i < dispc->feat->num_planes; ++i) {
-		if (clearmask & DSS_IRQ_PLANE_MASK(i)) {
+		if (clearmask & DSS_IRQ_PLANE_MASK(i))
 			dispc_k3_vid_write_irqstatus(dispc, i, clearmask);
-			top_clear |= BIT(4 + i);
-		}
 	}
-	if (dispc->feat->subrev == DISPC_K2G)
-		return;
 
-	dispc_write(dispc, DISPC_IRQSTATUS, top_clear);
+	dispc_write(dispc, DISPC_IRQSTATUS, dispc_read(dispc, DISPC_IRQSTATUS));
 
 	/* Flush posted writes */
 	dispc_read(dispc, DISPC_IRQSTATUS);
@@ -963,7 +963,7 @@ static void dispc_k3_set_irqenable(struct dispc_device *dispc,
 
 	old_mask = dispc_k3_read_irqenable(dispc);
 
-	/* clear the irqstatus for newly enabled irqs */
+	/* clear the irqstatus for irqs that will be enabled */
 	dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask);
 
 	for (i = 0; i < dispc->feat->num_vps; ++i) {
@@ -988,6 +988,9 @@ static void dispc_k3_set_irqenable(struct dispc_device *dispc,
 	if (main_disable)
 		dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable);
 
+	/* clear the irqstatus for irqs that were disabled */
+	dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & old_mask);
+
 	/* Flush posted writes */
 	dispc_read(dispc, DISPC_IRQENABLE_SET);
 }
@@ -1040,10 +1043,11 @@ struct dispc_bus_format {
 };
 
 static const struct dispc_bus_format dispc_bus_formats[] = {
+	{ MEDIA_BUS_FMT_RGB888_1X24,		24, false, 0 },
 	{ MEDIA_BUS_FMT_RGB444_1X12,		12, false, 0 },
 	{ MEDIA_BUS_FMT_RGB565_1X16,		16, false, 0 },
+	{ MEDIA_BUS_FMT_UYVY8_2X8,			16, false, 0 },
 	{ MEDIA_BUS_FMT_RGB666_1X18,		18, false, 0 },
-	{ MEDIA_BUS_FMT_RGB888_1X24,		24, false, 0 },
 	{ MEDIA_BUS_FMT_RGB101010_1X30,		30, false, 0 },
 	{ MEDIA_BUS_FMT_RGB121212_1X36,		36, false, 0 },
 	{ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,	18, true, SPWG_18 },
@@ -1198,7 +1202,7 @@ void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
 	const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state);
 	bool align, onoff, rf, ieo, ipc, ihs, ivs;
 	const struct dispc_bus_format *fmt;
-	u32 hsw, hfp, hbp, vsw, vfp, vbp;
+	u32 reg_val = 0u;
 
 	fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
 				    tstate->bus_flags);
@@ -1206,25 +1210,75 @@ void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
 	if (WARN_ON(!fmt))
 		return;
 
+	MSG("\033[34m dispc_vp_enable data_width:%d\033[0m", fmt->data_width);
 	dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width);
 
-	hfp = mode->hsync_start - mode->hdisplay;
-	hsw = mode->hsync_end - mode->hsync_start;
-	hbp = mode->htotal - mode->hsync_end;
-
-	vfp = mode->vsync_start - mode->vdisplay;
-	vsw = mode->vsync_end - mode->vsync_start;
-	vbp = mode->vtotal - mode->vsync_end;
-
-	dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
-		       FLD_VAL(hsw - 1, 7, 0) |
-		       FLD_VAL(hfp - 1, 19, 8) |
-		       FLD_VAL(hbp - 1, 31, 20));
-
-	dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V,
-		       FLD_VAL(vsw - 1, 7, 0) |
-		       FLD_VAL(vfp, 19, 8) |
-		       FLD_VAL(vbp, 31, 20));
+	if (dispc->tidss->bt656_enabled) {
+		u32 vfb1e, vfb2e, vfb1o, vfb2o, hb;
+/*
+	HBP DSS0_TIMING_H[31-20] HBP value + 1 Horizontal back porch
+	HFP DSS0_TIMING_H[19-8]  HFP value + 1 Horizontal front porch
+	HSW DSS0_TIMING_H[7-0]   HSW value + 1 Horizontal synchronization pulse width
+	VBP DSS0_TIMING_V[31-20] VBP value Vertical back porch
+	VFP DSS0_TIMING_V[19-8]  VFP value Vertical front porch
+	VSW DSS0_TIMING_V[7-0]   VSW value + 1 Vertical synchronization
+
+*/
+#if 1
+		// origin
+		vfb1e = mode->hsync_start - mode->hdisplay;    // HFP Horizontal front porch  1
+		vfb2e = mode->hsync_end   - mode->hsync_start; // HBP Horizontal back porch   14
+		vfb1o = mode->vsync_start - mode->vdisplay;    // VFP Vertical front porch
+		vfb2o = mode->vsync_end   - mode->vsync_start; // VBP Vertical back porch
+		hb = ((mode->htotal - mode->hdisplay) - 4)*2 - 1;  // (764 -720 -4)*2-1 = 79 = 0x4F
+		MSG("origin bt656_enabled = %d hw_videoport:%d", dispc->tidss->bt656_enabled, hw_videoport);
+		MSG("hsync_start:%d hsync_end:%d", mode->hsync_start,mode->hsync_end);
+		MSG("vsync_start:%d vsync_end:%d", mode->vsync_start,mode->vsync_end);
+		MSG("hdisplay:   %d vdisplay: %d", mode->hdisplay,mode->vdisplay);
+		MSG("vfb1e:%3d vfb2e:%3d vfb1o:%3d vfb2o:%3d", vfb1e，vfb2e，vfb1o，vfb2o);
+		MSG("Horizontal_blanking:%d", hb);
+
+		dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
+				FLD_VAL(hb & 0x00FF, 7, 0) |
+				FLD_VAL(vfb1e, 19, 8) |
+				FLD_VAL(vfb2e, 31, 20));
+
+		dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V,
+				FLD_VAL((hb >> 8), 3, 0) |
+				FLD_VAL(vfb1o, 19, 8) |
+				FLD_VAL(vfb2o, 31, 20));
+#endif
+		/*
+		dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
+				FLD_VAL(0x0B, 7, 0) |
+				FLD_VAL(0x01, 19, 8) |
+				FLD_VAL(0x0F, 31, 20));
+
+		dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V,
+				FLD_VAL(0x01, 3, 0) |
+				FLD_VAL(0x02, 19, 8) |
+				FLD_VAL(0x10, 31, 20));
+		*/
+	} else {
+		u32 hsw, hfp, hbp, vsw, vfp, vbp;
+
+		hfp = mode->hsync_start - mode->hdisplay;
+		hsw = mode->hsync_end - mode->hsync_start;
+		hbp = mode->htotal - mode->hsync_end;
+
+		vfp = mode->vsync_start - mode->vdisplay;
+		vsw = mode->vsync_end - mode->vsync_start;
+		vbp = mode->vtotal - mode->vsync_end;
+		dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
+				FLD_VAL(hsw - 1, 7, 0) |
+				FLD_VAL(hfp - 1, 19, 8) |
+				FLD_VAL(hbp - 1, 31, 20));
+	
+		dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V,
+				FLD_VAL(vsw - 1, 7, 0) |
+				FLD_VAL(vfp, 19, 8) |
+				FLD_VAL(vbp, 31, 20));
+	}
 
 	ivs = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
 
@@ -1255,13 +1309,110 @@ void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
 		       FLD_VAL(ihs, 13, 13) |
 		       FLD_VAL(ivs, 12, 12));
 
-	dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,
-		       FLD_VAL(mode->hdisplay - 1, 11, 0) |
-		       FLD_VAL(mode->vdisplay - 1, 27, 16));
+	if (dispc->tidss->bt656_enabled) {
+		u16 vdisplay = mode->vdisplay / 2;
+		u8 delta_lpp = 0x00;
+		MSG("vdisplay = vdisplay(%d) / 2 = %d", mode->vdisplay,vdisplay);
+
+		if ((mode->vdisplay & 0x01) == 0x01) {
+			MSG("\033[31m delta_lpp = 2 \033[0m\n");
+			delta_lpp = 0x02;		//Odd size is even size minus 1
+		} else {
+			vdisplay -= 1;
+		}
+		// LPP + (LPP + DELTA_LPP) + (VBP'No1 + VFP'No1) + (VBP'No2 + VFP'No2) == 625 lines
+		MSG("hdisplay: %d Number of pixels per line", delta_lpp);
+		MSG("vdisplay: %d Number of lines  per frame", vdisplay);
+		MSG("delta_lpp:%d ", delta_lpp);
+		dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,
+				FLD_VAL(mode->hdisplay - 1, 11, 0) | FLD_VAL(delta_lpp, 15, 14) |
+				FLD_VAL(vdisplay, 27, 16));
+		if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
+			VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, 1, 22, 22);
+		}
+	} else {
+		dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,
+				FLD_VAL(mode->hdisplay - 1, 11, 0) |
+				FLD_VAL(mode->vdisplay - 1, 27, 16));
+	}
 
 	VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0);
+	
+	reg_val = dispc_vp_read(dispc, hw_videoport, DISPC_VP_POL_FREQ);
+	printk("\n[%s %d] wpq hw_videoport=%d, DISPC_VP_POL_FREQ=0x%08x\n",__func__,__LINE__, hw_videoport, reg_val);
+	reg_val = dispc_vp_read(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN);
+	printk("[%s %d] wpq hw_videoport=%d, DISPC_VP_SIZE_SCREEN=0x%08x\n",__func__,__LINE__, hw_videoport, reg_val);
+	reg_val = dispc_vp_read(dispc, hw_videoport, DISPC_VP_CONTROL);
+	printk("[%s %d] wpq hw_videoport=%d, DISPC_VP_CONTROL=0x%08x\n",__func__,__LINE__, hw_videoport, reg_val);
+	reg_val = dispc_vp_read(dispc, hw_videoport, DISPC_VP_CONFIG);
+	printk("[%s %d] wpq hw_videoport=%d, DISPC_VP_CONFIG=0x%08x\n",__func__,__LINE__, hw_videoport, reg_val);
 }
 
+#if 1
+//debug++
+void dispc_get_hsw(struct dispc_device *dispc, u32 hw_videoport, u32 *hsw)
+{
+	*hsw = VP_REG_GET(dispc, hw_videoport, DISPC_VP_TIMING_H, 7, 0) + 1;
+}
+
+void dispc_set_hsw(struct dispc_device *dispc, u32 hw_videoport, u32 hsw)
+{
+	VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_TIMING_H, hsw - 1, 7, 0);
+}
+
+void dispc_get_hfp(struct dispc_device *dispc, u32 hw_videoport, u32 *hfp)
+{
+	*hfp = VP_REG_GET(dispc, hw_videoport, DISPC_VP_TIMING_H, 19, 8) + 1;
+}
+
+void dispc_set_hfp(struct dispc_device *dispc, u32 hw_videoport, u32 hfp)
+{
+	VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_TIMING_H, hfp - 1, 19, 8);
+}
+
+void dispc_get_hbp(struct dispc_device *dispc, u32 hw_videoport, u32 *hbp)
+{
+	*hbp = VP_REG_GET(dispc, hw_videoport, DISPC_VP_TIMING_H, 31, 20) + 1;
+}
+
+void dispc_set_hbp(struct dispc_device *dispc, u32 hw_videoport, u32 hfp)
+{
+	VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_TIMING_H, hfp - 1, 31, 20);
+}
+
+void dispc_get_vsw(struct dispc_device *dispc, u32 hw_videoport, u32 *vsw)
+{
+	*vsw = VP_REG_GET(dispc, hw_videoport, DISPC_VP_TIMING_V, 7, 0) + 1;
+}
+
+void dispc_set_vsw(struct dispc_device *dispc, u32 hw_videoport, u32 vsw)
+{
+	VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_TIMING_V, vsw - 1, 7, 0);
+}
+
+void  dispc_get_vfp(struct dispc_device *dispc, u32 hw_videoport, u32 *vfp)
+{
+	*vfp = VP_REG_GET(dispc, hw_videoport, DISPC_VP_TIMING_V, 19, 8) + 1;
+}
+
+void dispc_set_vfp(struct dispc_device *dispc, u32 hw_videoport, u32 vfp)
+{
+	VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_TIMING_V, vfp - 1, 19, 8);
+}
+
+void  dispc_get_vbp(struct dispc_device *dispc, u32 hw_videoport, u32 *vbp)
+{
+	*vbp = VP_REG_GET(dispc, hw_videoport, DISPC_VP_TIMING_V, 27, 16) + 1;
+}
+
+void dispc_set_vbp(struct dispc_device *dispc, u32 hw_videoport, u32 vbp)
+{
+	VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_TIMING_V, vbp - 1, 27, 16);
+}
+
+#endif
+
+
 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport)
 {
 	VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0);
@@ -1383,10 +1534,6 @@ enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
 	if (mode->vdisplay > 4096)
 		return MODE_BAD;
 
-	/* TODO: add interlace support */
-	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
-		return MODE_NO_INTERLACE;
-
 	/*
 	 * Enforce the output width is divisible by 2. Actually this
 	 * is only needed in following cases:
@@ -1406,14 +1553,16 @@ enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
 	vsw = mode->vsync_end - mode->vsync_start;
 	vbp = mode->vtotal - mode->vsync_end;
 
-	if (hsw < 1 || hsw > 256 ||
-	    hfp < 1 || hfp > 4096 ||
-	    hbp < 1 || hbp > 4096)
-		return MODE_BAD_HVALUE;
+	if (!dispc->tidss->bt656_enabled) {
+		if (hsw < 1 || hsw > 256 ||
+		    hfp < 1 || hfp > 4096 ||
+		    hbp < 1 || hbp > 4096)
+			return MODE_BAD_HVALUE;
 
-	if (vsw < 1 || vsw > 256 ||
-	    vfp > 4095 || vbp > 4095)
-		return MODE_BAD_VVALUE;
+		if (vsw < 1 || vsw > 256 ||
+		    vfp > 4095 || vbp > 4095)
+			return MODE_BAD_VVALUE;
+	}
 
 	if (dispc->memory_bandwidth_limit) {
 		if (!dispc->tidss->shared_mode ||
@@ -1501,12 +1650,12 @@ static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc,
 				      u32 hw_plane, u32 hw_videoport,
 				      u32 x, u32 y, u32 layer)
 {
-	OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
-			hw_plane, 4, 1);
-	OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
-			x, 17, 6);
-	OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
-			y, 30, 19);
+	//Setup test pattern
+	//OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_CONFIG, 1, 1, 1);
+
+	OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), hw_plane, 4, 1);
+	OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), x, 17, 6);
+	OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), y, 30, 19);
 }
 
 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc,
@@ -1610,15 +1759,15 @@ void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regval)
 	dispc_csc_offset_regval(csc, regval);
 }
 
-__maybe_unused static
+static
 void dispc_csc_rgb2yuv_regval(const struct dispc_csc_coef *csc, u32 *regval)
 {
 	regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]);
-	regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]);
-	regval[2] = CVAL(csc->m[CSC_CRG], csc->m[CSC_CRB]);
-	regval[3] = CVAL(csc->m[CSC_CBR], csc->m[CSC_CBG]);
-	regval[4] = CVAL(csc->m[CSC_CBB], 0);
-
+	regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CBR]);
+	regval[2] = CVAL(csc->m[CSC_CBG], csc->m[CSC_CBB]);
+	regval[3] = CVAL(csc->m[CSC_CRR], csc->m[CSC_CRG]);
+	regval[4] = CVAL(csc->m[CSC_CRB], 0);
+	//pr_info("csc->m[CSS_CbR] %x fld_val %x \n", csc->m[CSC_CBR], FLD_VAL(-38, 26, 16));
 	dispc_csc_offset_regval(csc, regval);
 }
 
@@ -1726,6 +1875,19 @@ static const struct dispc_csc_coef csc_yuv2rgb_bt709_lim = {
 	"BT.709 Limited",
 };
 
+
+/* YUV -> RGB, ITU-R BT.601, limited range */
+static const struct dispc_csc_coef csc_rgb2yuv_bt601_lim = {
+	dispc_csc_rgb2yuv_regval,
+	{ 66,  129,  25,	/* ry, rcb, rcr |0.257  0.504  0.098|*/
+	 -38,  -75, 112,	/* gy, gcb, gcr |-0.148 -0.291 0.439|*/
+	  112, -94, -18, },	/* by, bcb, bcr |0.439  -0.368  -0.071|*/
+	{  0,    0,  0, },
+	{ 256, 2048, 2048, },	/* limited range */
+	CLIP_FULL_RANGE,
+	"BT.601 Limited",
+};
+
 static const struct {
 	enum drm_color_encoding encoding;
 	enum drm_color_range range;
@@ -1739,6 +1901,8 @@ static const struct {
 	  &csc_yuv2rgb_bt709_full, },
 	{ DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE,
 	  &csc_yuv2rgb_bt709_lim, },
+	{ DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_LIMITED_RANGE,
+	  &csc_rgb2yuv_bt601_lim, },
 };
 
 static const
@@ -2247,18 +2411,27 @@ void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
 	u32 fb_width = state->fb->pitches[0] / cpp;
 	dma_addr_t dma_addr = dispc_plane_state_dma_addr(state);
 	struct dispc_scaling_params scale;
+	struct drm_crtc_state *crtc_state = NULL;
+	bool ilace = false;
 
 	dispc_vid_calc_scaling(dispc, state, &scale, lite);
 
 	dispc_plane_set_pixel_format(dispc, hw_plane, fourcc);
 
+	if(state->crtc && state->state) {
+		crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
+		if(crtc_state && (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)) {
+			ilace = true;
+		}
+	}
+
 	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff);
 	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32);
-	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff);
-	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32);
+	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, (dma_addr + (ilace ? fb_width*cpp : 0)) & 0xffffffff);
+	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)(dma_addr + (ilace ? fb_width*cpp : 0)) >> 32);
 
 	dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,
-			(scale.in_w - 1) | ((scale.in_h - 1) << 16));
+			(scale.in_w - 1) | ((scale.in_h/(ilace ? 2 : 1) - 1) << 16));
 
 	/* For YUV422 format we use the macropixel size for pixel inc */
 	if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY)
@@ -2270,7 +2443,7 @@ void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
 
 	dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC,
 			pixinc(1 + (scale.yinc * fb_width -
-				    scale.xinc * scale.in_w),
+					scale.xinc * scale.in_w) + (ilace ? fb_width : 0),
 			       cpp));
 
 	if (state->fb->format->num_planes == 2) {
@@ -2467,12 +2640,22 @@ static void dispc_plane_init(struct dispc_device *dispc)
 static void dispc_vp_init(struct dispc_device *dispc)
 {
 	unsigned int i;
+	u32 reg_val = 0u;
 
-	dev_dbg(dispc->dev, "%s()\n", __func__);
+	/* DISPC_AM62P51=3, DISPC_AM62P54=4 */
+	printk("[%s %d] Wpq subrev=%d\n", __func__, __LINE__, dispc->feat->subrev);
 
 	/* Enable the gamma Shadow bit-field for all VPs*/
-	for (i = 0; i < dispc->feat->num_vps; i++)
-		VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2);
+	for (i = 0; i < dispc->feat->num_vps; i++) {
+		if (!dispc->tidss->bt656_enabled)
+			VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2);
+
+		if (dispc->tidss->bt656_enabled)
+			VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 20, 20);
+
+		reg_val = dispc_vp_read(dispc, i, DISPC_VP_CONFIG);
+		printk("[%s %d] wpq i=%d, DISPC_VP_CONFIG=0x%08x",__func__,__LINE__, i, reg_val);
+	}
 }
 
 static void dispc_initial_config(struct dispc_device *dispc)
@@ -2754,9 +2937,11 @@ static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
 
 	csc->to_regval(csc, regval);
 
-	for (i = 0; i < ARRAY_SIZE(regval); i++)
+	for (i = 0; i < ARRAY_SIZE(regval); i++) {
+		//pr_info("CSC: Writing at reg: %x value: %x\n", dispc_vp_csc_coef_reg[i], regval[i]);
 		dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i],
 			       regval[i]);
+	}
 }
 
 static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
@@ -2797,11 +2982,23 @@ static void dispc_vp_set_color_mgmt(struct dispc_device *dispc,
 
 	if (state->ctm)
 		ctm = (struct drm_color_ctm *)state->ctm->data;
-
+	
 	if (dispc->feat->subrev == DISPC_K2G)
 		dispc_k2g_vp_set_ctm(dispc, hw_videoport, ctm);
 	else
 		dispc_k3_vp_set_ctm(dispc, hw_videoport, ctm);
+
+	if (dispc->tidss->bt656_enabled) 
+	{
+		u32 reg_val = 0u;
+		u8 colorconvenable = 1;
+		dispc_k3_vp_write_csc(dispc, hw_videoport, dispc_csc_table[4].csc);
+		
+		VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, colorconvenable, 24, 24);
+
+		reg_val = dispc_vp_read(dispc, hw_videoport, DISPC_VP_CONFIG);
+		printk("[%s %d] wpq hw_videoport=%d, DISPC_VP_CONFIG=0x%08x",__func__,__LINE__, hw_videoport, reg_val);
+	}
 }
 
 static int get_vp_idx_from_vp(const char *vp_name)
@@ -3078,8 +3275,12 @@ static void dispc_init_errata(struct dispc_device *dispc)
  */
 static void dispc_softreset_k2g(struct dispc_device *dispc)
 {
+	unsigned long flags;
+
+	spin_lock_irqsave(&dispc->tidss->irq_lock, flags);
 	dispc_set_irqenable(dispc, 0);
 	dispc_read_and_clear_irqstatus(dispc);
+	spin_unlock_irqrestore(&dispc->tidss->irq_lock, flags);
 
 	for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx)
 		VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0);
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h
index cc39ed5f7..ef1459074 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.h
+++ b/drivers/gpu/drm/tidss/tidss_dispc.h
@@ -147,4 +147,20 @@ void dispc_remove(struct tidss_device *tidss);
 
 void dispc_splash_fini(struct dispc_device *dispc);
 
+#if 1
+void dispc_get_hsw(struct dispc_device *dispc, u32 hw_videoport, u32 *hsw);
+void dispc_set_hsw(struct dispc_device *dispc, u32 hw_videoport, u32 hsw);
+void dispc_get_hfp(struct dispc_device *dispc, u32 hw_videoport, u32 *hfp);
+void dispc_set_hfp(struct dispc_device *dispc, u32 hw_videoport, u32 hfp);
+void dispc_get_hbp(struct dispc_device *dispc, u32 hw_videoport, u32 *hbp);
+void dispc_set_hbp(struct dispc_device *dispc, u32 hw_videoport, u32 hbp);
+
+void dispc_get_vsw(struct dispc_device *dispc, u32 hw_videoport, u32 *vsw);
+void dispc_set_vsw(struct dispc_device *dispc, u32 hw_videoport, u32 vsw);
+void  dispc_get_vfp(struct dispc_device *dispc, u32 hw_videoport, u32 *vfp);
+void dispc_set_vfp(struct dispc_device *dispc, u32 hw_videoport, u32 vfp);
+void  dispc_get_vbp(struct dispc_device *dispc, u32 hw_videoport, u32 *vb);
+void dispc_set_vbp(struct dispc_device *dispc, u32 hw_videoport, u32 vb);
+#endif
+
 #endif
diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tidss_drv.c
index 274a3d775..8d5f8b15f 100644
--- a/drivers/gpu/drm/tidss/tidss_drv.c
+++ b/drivers/gpu/drm/tidss/tidss_drv.c
@@ -26,8 +26,19 @@
 #include "tidss_irq.h"
 #include "tidss_oldi.h"
 
-/* Power management */
 
+#define USE_SYSFS_DEBUG 1
+#define DEBUG 1
+#if DEBUG
+static int dbg_level = 1;
+#else
+static int dbg_level = 0;
+#endif
+#define MSG(fmt, args...) printk("\033[33m<tidss> "fmt" %s", ##args,"\033[0m\n")
+#define ERR(fmt, args...) printk(KERN_ERR "\033[31m<tidss>err: "fmt" %s", ##args,"\033[0m\n")
+#define DBG(fmt, args...) if (dbg_level) printk("\033[33m<tidss> "fmt" %s", ##args,"\033[0m\n")
+
+/* Power management */
 int tidss_runtime_get(struct tidss_device *tidss)
 {
 	int r;
@@ -228,6 +239,114 @@ static void check_for_simplefb_device(struct tidss_device *tidss)
 	}
 }
 
+#if USE_SYSFS_DEBUG
+
+static ssize_t store_tp2803fe_set_HBP(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct tidss_device *tidss = platform_get_drvdata(pdev);
+	sscanf(buf, "%d", &val);
+	dispc_set_hsw(tidss->dispc, 0, val);
+	return strnlen(buf, count);
+}
+
+static ssize_t store_tp2803fe_get_HBP(struct device *dev,struct device_attribute *attr, char *buf)
+{
+	u32 ret_val;
+	u32 hbp;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct tidss_device *tidss = platform_get_drvdata(pdev);
+
+	dispc_get_hbp(tidss->dispc, 0, &hbp);
+
+	MSG("hbp:%d", hbp);
+
+	return sprintf(buf, "0x%lX\n", (unsigned int)hbp);
+}
+
+static DEVICE_ATTR(HBP, (S_IWUSR|S_IWGRP), store_tp2803fe_get_HBP,store_tp2803fe_set_HBP);
+
+static ssize_t store_tp2803fe_set_HFP(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct tidss_device *tidss = platform_get_drvdata(pdev);
+	sscanf(buf, "%d", &val);
+	dispc_set_hfp(tidss->dispc, 1, val);
+	return strnlen(buf, count);
+}
+static DEVICE_ATTR(HFP, (S_IWUSR|S_IWGRP), NULL,store_tp2803fe_set_HFP);
+
+static ssize_t store_tp2803fe_set_VBP(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct tidss_device *tidss = platform_get_drvdata(pdev);
+	sscanf(buf, "%d", &val);
+	dispc_set_vbp(tidss->dispc, 0, val);
+	return strnlen(buf, count);
+}
+static DEVICE_ATTR(VBP, (S_IWUSR|S_IWGRP), NULL,store_tp2803fe_set_VBP);
+
+static ssize_t store_tp2803fe_set_VFP(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct tidss_device *tidss = platform_get_drvdata(pdev);
+	sscanf(buf, "%d", &val);
+	dispc_set_vfp(tidss->dispc, 1, val);
+	return strnlen(buf, count);
+}
+static DEVICE_ATTR(VFP, (S_IWUSR|S_IWGRP), NULL,store_tp2803fe_set_VFP);
+
+static ssize_t dispc_show_regs(struct device *dev,struct device_attribute *attr, char *buf)
+{
+	u32 ret_val = 0;
+	u32 hsw, hfp, hbp, vsw, vfp, vbp;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct tidss_device *tidss = platform_get_drvdata(pdev);
+
+	printk(KERN_ERR"	HBP DSS0_TIMING_H[31-20] HBP value + 1 Horizontal back porch");
+	printk(KERN_ERR"	HFP DSS0_TIMING_H[19-8]  HFP value + 1 Horizontal front porch");
+	printk(KERN_ERR"	VBP DSS0_TIMING_V[31-20] VBP value + 1 Vertical back porch");
+	printk(KERN_ERR"	VFP DSS0_TIMING_V[19-8]  VFP value + 1 Vertical front porch");
+	printk(KERN_ERR"	| HSW| VSW | VBP | HBP |");
+
+	dispc_get_hsw(tidss->dispc, 0, &hsw);
+	dispc_get_hfp(tidss->dispc, 0, &hfp);
+	dispc_get_hbp(tidss->dispc, 0, &hbp);
+	dispc_get_vsw(tidss->dispc, 0, &vsw);
+	dispc_get_vfp(tidss->dispc, 0, &vfp);
+	dispc_get_vbp(tidss->dispc, 0, &vbp);
+
+	printk("hsw:%d hfp:%d hbp:%d", hsw, hfp, hbp);
+	printk("vsw:%d vfp:%d vbp:%d", vsw, vfp, vbp);
+
+	return sprintf(buf, "0x%lX\n", ret_val);
+}
+static DEVICE_ATTR(dispc_regs, S_IRUGO, dispc_show_regs, NULL);
+
+
+static struct attribute *tidss_sysfs_entries[] = {
+	&dev_attr_HBP.attr,
+	&dev_attr_HFP.attr,
+	&dev_attr_VBP.attr,
+	&dev_attr_VFP.attr,
+	&dev_attr_dispc_regs.attr,
+	NULL
+};
+
+static const struct attribute_group tidss_attribute_group = {
+	.name = NULL,		/* put in device directory */
+	.attrs = tidss_sysfs_entries,
+};
+#endif
+
 static int tidss_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -236,7 +355,9 @@ static int tidss_probe(struct platform_device *pdev)
 	int ret;
 	int irq;
 
-	dev_dbg(dev, "%s\n", __func__);
+	// 30200000.dss & 30220000.dss 
+	//printk("[%s %d] name=%s Here\n",__func__, __LINE__, pdev->name);
+	MSG(" 0 tidss_probe DRM 设备:%s begin",pdev->name); //debug++
 
 	tidss = devm_drm_dev_alloc(&pdev->dev, &tidss_driver,
 				   struct tidss_device, ddev);
@@ -250,11 +371,12 @@ static int tidss_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, tidss);
 
-	spin_lock_init(&tidss->wait_lock);
+	spin_lock_init(&tidss->irq_lock);
 
+	tidss->bt656_enabled = device_property_read_bool(dev, "ti,bt656-mode");
 	tidss->shared_mode = device_property_read_bool(dev, "ti,dss-shared-mode");
 	check_for_simplefb_device(tidss);
-
+	
 	if (!tidss->shared_mode) {
 		/* powering up associated OLDI domains */
 		ret = tidss_attach_pm_domains(tidss);
@@ -283,7 +405,7 @@ static int tidss_probe(struct platform_device *pdev)
 		dispc_runtime_resume(tidss->dispc);
 #endif
 	}
-
+ 
 	ret = tidss_modeset_init(tidss);
 	if (ret < 0) {
 		if (ret != -EPROBE_DEFER)
@@ -308,6 +430,7 @@ static int tidss_probe(struct platform_device *pdev)
 
 	drm_mode_config_reset(ddev);
 
+	MSG("tidss_probe->drm_dev_register"); //debug++
 	ret = drm_dev_register(ddev, 0);
 	if (ret) {
 		dev_err(dev, "failed to register DRM device\n");
@@ -318,6 +441,13 @@ static int tidss_probe(struct platform_device *pdev)
 
 	dev_dbg(dev, "%s done\n", __func__);
 
+#if USE_SYSFS_DEBUG
+	ret = sysfs_create_group(&pdev->dev.kobj,&tidss_attribute_group);
+	if (ret) {
+		printk(KERN_ERR"sysfs_create_group failed\n");
+	}
+#endif
+	MSG(" 0 tidss_probe DRM 设备:%s end",pdev->name); //debug++
 	return 0;
 
 err_irq_uninstall:
diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h
index 4cca90f0e..a00009a08 100644
--- a/drivers/gpu/drm/tidss/tidss_drv.h
+++ b/drivers/gpu/drm/tidss/tidss_drv.h
@@ -33,8 +33,9 @@ struct tidss_device {
 
 	unsigned int irq;
 
-	spinlock_t wait_lock;	/* protects the irq masks */
-	dispc_irq_t irq_mask;	/* enabled irqs in addition to wait_list */
+	/* protects the irq masks field and irqenable/irqstatus registers */
+	spinlock_t irq_lock;
+	dispc_irq_t irq_mask;   /* enabled irqs */
 
 	bool shared_mode; /* DSS resources shared between remote core and Linux */
 	/* 1: VP owned by Linux 0: VP is owned by remote and shared with Linux */
@@ -47,6 +48,7 @@ struct tidss_device {
 
 	u32 boot_enabled_vp_mask;
 	bool simplefb_enabled;
+	bool bt656_enabled;
 };
 
 #define to_tidss(__dev) container_of(__dev, struct tidss_device, ddev)
diff --git a/drivers/gpu/drm/tidss/tidss_encoder.c b/drivers/gpu/drm/tidss/tidss_encoder.c
index 17a86bed8..e56a49516 100644
--- a/drivers/gpu/drm/tidss/tidss_encoder.c
+++ b/drivers/gpu/drm/tidss/tidss_encoder.c
@@ -115,7 +115,8 @@ int tidss_encoder_create(struct tidss_device *tidss,
 		dev_err(tidss->dev, "bridge_connector create failed\n");
 		return PTR_ERR(connector);
 	}
-
+	
+	connector->interlace_allowed = true;
 	ret = drm_connector_attach_encoder(connector, enc);
 	if (ret) {
 		dev_err(tidss->dev, "attaching encoder to connector failed\n");
diff --git a/drivers/gpu/drm/tidss/tidss_irq.c b/drivers/gpu/drm/tidss/tidss_irq.c
index 604334ef5..1104ad74d 100644
--- a/drivers/gpu/drm/tidss/tidss_irq.c
+++ b/drivers/gpu/drm/tidss/tidss_irq.c
@@ -15,10 +15,9 @@
 #include "tidss_irq.h"
 #include "tidss_plane.h"
 
-/* call with wait_lock and dispc runtime held */
 static void tidss_irq_update(struct tidss_device *tidss)
 {
-	assert_spin_locked(&tidss->wait_lock);
+	assert_spin_locked(&tidss->irq_lock);
 
 	dispc_set_irqenable(tidss->dispc, tidss->irq_mask);
 }
@@ -31,11 +30,11 @@ void tidss_irq_enable_vblank(struct drm_crtc *crtc)
 	u32 hw_videoport = tcrtc->hw_videoport;
 	unsigned long flags;
 
-	spin_lock_irqsave(&tidss->wait_lock, flags);
+	spin_lock_irqsave(&tidss->irq_lock, flags);
 	tidss->irq_mask |= DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) |
 			   DSS_IRQ_VP_VSYNC_ODD(hw_videoport);
 	tidss_irq_update(tidss);
-	spin_unlock_irqrestore(&tidss->wait_lock, flags);
+	spin_unlock_irqrestore(&tidss->irq_lock, flags);
 }
 
 void tidss_irq_disable_vblank(struct drm_crtc *crtc)
@@ -46,11 +45,11 @@ void tidss_irq_disable_vblank(struct drm_crtc *crtc)
 	u32 hw_videoport = tcrtc->hw_videoport;
 	unsigned long flags;
 
-	spin_lock_irqsave(&tidss->wait_lock, flags);
+	spin_lock_irqsave(&tidss->irq_lock, flags);
 	tidss->irq_mask &= ~(DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) |
 			     DSS_IRQ_VP_VSYNC_ODD(hw_videoport));
 	tidss_irq_update(tidss);
-	spin_unlock_irqrestore(&tidss->wait_lock, flags);
+	spin_unlock_irqrestore(&tidss->irq_lock, flags);
 }
 
 static irqreturn_t tidss_irq_handler(int irq, void *arg)
@@ -60,7 +59,9 @@ static irqreturn_t tidss_irq_handler(int irq, void *arg)
 	unsigned int id;
 	dispc_irq_t irqstatus;
 
+	spin_lock(&tidss->irq_lock);
 	irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc);
+	spin_unlock(&tidss->irq_lock);
 
 	for (id = 0; id < tidss->num_crtcs; id++) {
 		struct drm_crtc *crtc = tidss->crtcs[id];
@@ -78,9 +79,14 @@ static irqreturn_t tidss_irq_handler(int irq, void *arg)
 			tidss_crtc_error_irq(crtc, irqstatus);
 	}
 
-	if (irqstatus & DSS_IRQ_DEVICE_OCP_ERR)
-		dev_err_ratelimited(tidss->dev, "OCP error\n");
+	for (unsigned int i = 0; i < tidss->num_planes; ++i) 
+	{
+		struct drm_plane *plane = tidss->planes[i];
+		struct tidss_plane *tplane = to_tidss_plane(plane);
 
+		if (irqstatus & DSS_IRQ_PLANE_FIFO_UNDERFLOW(tplane->hw_plane_id))
+			tidss_plane_error_irq(plane, irqstatus);
+	}
 	return IRQ_HANDLED;
 }
 
@@ -88,9 +94,9 @@ void tidss_irq_resume(struct tidss_device *tidss)
 {
 	unsigned long flags;
 
-	spin_lock_irqsave(&tidss->wait_lock, flags);
+	spin_lock_irqsave(&tidss->irq_lock, flags);
 	tidss_irq_update(tidss);
-	spin_unlock_irqrestore(&tidss->wait_lock, flags);
+	spin_unlock_irqrestore(&tidss->irq_lock, flags);
 }
 
 int tidss_irq_install(struct drm_device *ddev, unsigned int irq)
@@ -105,7 +111,7 @@ int tidss_irq_install(struct drm_device *ddev, unsigned int irq)
 	if (ret)
 		return ret;
 
-	tidss->irq_mask = DSS_IRQ_DEVICE_OCP_ERR;
+	tidss->irq_mask = 0;
 
 	for (unsigned int i = 0; i < tidss->num_crtcs; ++i) {
 		struct tidss_crtc *tcrtc = to_tidss_crtc(tidss->crtcs[i]);
@@ -115,6 +121,13 @@ int tidss_irq_install(struct drm_device *ddev, unsigned int irq)
 		tidss->irq_mask |= DSS_IRQ_VP_FRAME_DONE(tcrtc->hw_videoport);
 	}
 
+	for (unsigned int i = 0; i < tidss->num_planes; ++i) 
+	{
+	    struct tidss_plane *tplane = to_tidss_plane(tidss->planes[i]);
+	
+	    tidss->irq_mask |= DSS_IRQ_PLANE_FIFO_UNDERFLOW(tplane->hw_plane_id);
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/tidss/tidss_irq.h b/drivers/gpu/drm/tidss/tidss_irq.h
index b512614d5..dd61f645f 100644
--- a/drivers/gpu/drm/tidss/tidss_irq.h
+++ b/drivers/gpu/drm/tidss/tidss_irq.h
@@ -19,15 +19,13 @@
  * bit use   |D  |fou|FEOL|FEOL|FEOL|FEOL|  UUUU  |          |
  * bit number|0  |1-3|4-7 |8-11|  12-19  | 20-23  |  24-31   |
  *
- * device bits:	D = OCP error
+ * device bits:	D = Unused
  * WB bits:	f = frame done wb, o = wb buffer overflow,
  *		u = wb buffer uncomplete
  * vp bits:	F = frame done, E = vsync even, O = vsync odd, L = sync lost
  * plane bits:	U = fifo underflow
  */
 
-#define DSS_IRQ_DEVICE_OCP_ERR			BIT(0)
-
 #define DSS_IRQ_DEVICE_FRAMEDONEWB		BIT(1)
 #define DSS_IRQ_DEVICE_WBBUFFEROVERFLOW		BIT(2)
 #define DSS_IRQ_DEVICE_WBUNCOMPLETEERROR	BIT(3)
diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c
index a0e494c80..831f8165c 100644
--- a/drivers/gpu/drm/tidss/tidss_kms.c
+++ b/drivers/gpu/drm/tidss/tidss_kms.c
@@ -175,6 +175,8 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss)
 			}
 		}
 
+		dev_warn(dev, "Bridge interlace_allowed %d\n", bridge->interlace_allowed);
+		bridge->interlace_allowed = true;
 		pipes[num_pipes].hw_videoport = i;
 		pipes[num_pipes].bridge = bridge;
 		pipes[num_pipes].enc_type = enc_type;
diff --git a/drivers/gpu/drm/tidss/tidss_plane.c b/drivers/gpu/drm/tidss/tidss_plane.c
index 68fed531f..3877c0b5a 100644
--- a/drivers/gpu/drm/tidss/tidss_plane.c
+++ b/drivers/gpu/drm/tidss/tidss_plane.c
@@ -19,6 +19,13 @@
 
 /* drm_plane_helper_funcs */
 
+void tidss_plane_error_irq(struct drm_plane *plane, u64 irqstatus)
+{
+    struct tidss_plane *tplane = to_tidss_plane(plane);
+    dev_err_ratelimited(plane->dev->dev, "Plane%u underflow (irq %llx)\n",
+                        tplane->hw_plane_id, irqstatus);
+}
+
 static int tidss_plane_atomic_check(struct drm_plane *plane,
 				    struct drm_atomic_state *state)
 {
@@ -123,7 +130,9 @@ static void tidss_plane_atomic_update(struct drm_plane *plane,
 	}
 
 	hw_videoport = to_tidss_crtc(new_state->crtc)->hw_videoport;
-
+	/* Not sure how safe this is. Hopefully it does not harm to update the pointer in the state structure with the valid one */
+	if (new_state->state == NULL)
+		new_state->state = state;
 	dispc_plane_setup(tidss->dispc, tplane->hw_plane_id, new_state, hw_videoport);
 }
 
diff --git a/drivers/gpu/drm/tidss/tidss_plane.h b/drivers/gpu/drm/tidss/tidss_plane.h
index e933e158b..aecaf2728 100644
--- a/drivers/gpu/drm/tidss/tidss_plane.h
+++ b/drivers/gpu/drm/tidss/tidss_plane.h
@@ -22,4 +22,6 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,
 				       u32 crtc_mask, const u32 *formats,
 				       u32 num_formats);
 
+void tidss_plane_error_irq(struct drm_plane *plane, u64 irqstatus);
+
 #endif

0 Yong Zhang 6 days ago in reply to Donghui Peng

TI__Genius 17111 points

Dear Donghui.

per discussion, we may need your input for below two items to check the issue and code.

Donghui Peng said:
my board: AM62P DPI => BT6576 => TP2803 => CVBS panel

1. what is the parameter of the display, such as, Hight, width, HBP, VBP.... like below.

2. per discussed, there is one issue even if pattern is displayed, Line and field is out of sync. Please help clarify this point in detail.

thanks a lot!

yong

0 Donghui Peng 6 days ago in reply to Yong Zhang

Prodigy 60 points

// calc from AM62Px Technical Reference Manual.pdf  Page 1919
    dispc_vp_enable(...) {
    ...
    vfb1e = mode->hsync_start - mode->hdisplay;    // Vertical field blanking No.1 for Even Field
    vfb2e = mode->hsync_end   - mode->hsync_start; // Vertical field blanking No.2 for Even Field
	vfb1o = mode->vsync_start - mode->vdisplay;    // Vertical field blanking No.1 for Odd Field
	vfb2o = mode->vsync_end   - mode->vsync_start; // Vertical field blanking No.2 for Odd Field
	hb = ((mode->htotal - mode->hdisplay) - 4)*2 - 1;  // (764 -720 -4)*2-1 = 79 = 0x4F
	
	dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
				FLD_VAL(hb & 0x00FF, 7, 0) |
					FLD_VAL(vfb1e, 19, 8) |
				FLD_VAL(vfb2e, 31, 20));
				
	dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V,
				FLD_VAL((hb >> 8), 3, 0) |
				FLD_VAL(vfb1o, 19, 8) |
				FLD_VAL(vfb2o, 31, 20));
	...
	}