AUDIO-AM62D-EVM: Differences in DDR settings between AM62D-EVM and SK-AM62A-LP

The default AM62A DDR frequency is 1866MHz, and the default AM62D DDR frequency is 1600MHz.  The bus clock frequency is set in the device tree file (for example, for AM62A, it is in u-boot\arch\arm\dts\k3-am62a-ddr-1866mhz-32bit.dtsi in SDK10)

If you check these files, there will be a line at the top similar to:

#define DDRSS_PLL_FREQUENCY_2 933000000

The PLL is set to 1/2 of the bus frequency, so this represents 1866MHz

If you check the appropriate files in each of the SDK revisions, I suspect you will see a difference in the one with the slightly slower performance.

Regards,

James

Hi James,

Thank you for your reply.

I checked the DDR settings for both SDKs.
<sdk>\source\drivers\ddr\v1\soc\<am62dx or am62ax>\

The frequency in "board_ddrReginit.h" was the same, but the PLL settings were different.
What impact does this have? It wasn't mentioned in the TRM.

AM62A:
#define DDRSS_PLL_FHS_CNT 5
#define DDRSS_PLL_FREQUENCY_1 933333333
#define DDRSS_PLL_FREQUENCY_2 933333333

AM62D:
#define DDRSS_PLL_FHS_CNT 3
#define DDRSS_PLL_FREQUENCY_1 933333333
#define DDRSS_PLL_FREQUENCY_2 933333333

The frequencies in "ddr_soc.h" were the same.
#define DDR_MHZ (1600U) /* DDR clock speed in MHz */

Best regards,
O.H

O.H said:

The frequency in "board_ddrReginit.h" was the same, but the PLL settings were different.

What PLL settings were different?  The FHS_CNT parameter is just a loop count, it doesn't have anything to do with the actual frequency.

If you have JTAG access, can you run Get_All_PLL_Configuration() GEL script to dump and parse all of the PLL settings?

If that is not available, you can try reading the DDR PLL12 registers at 0x0068C000-0x0068C060 to determine the multiplier and divider values of the PLL

Regards,

James

Hi James,

JJD said:

If you have JTAG access, can you run Get_All_PLL_Configuration() GEL script to dump and parse all of the PLL settings?

If that is not available, you can try reading the DDR PLL12 registers at 0x0068C000-0x0068C060 to determine the multiplier and divider values of the PLL

Both EVMs were configured to run the C7x at 500MHz and the same .out file was written. The PLL register values ​​were compared before and after running "system_init()".
The results showed that DDRSS was not found, but there were no differences in PLL12.
- CFG_pll1_HSDIV_CTRL6: There was a change before and after running "system_init()", but no differences between the EVMs.
- CFG_pll2/5/7/8/12_CAL_STAT: There was no change before and after running "system_init()", but there were differences between the EVMs.
- There were no differences in all other registers.

Best regards,
O.H

Most of the values above just represent calibration status, these differences wouldn't affect performance. If none of the other PLL registers are different, then the bus configuration is the same between these two environments.

How are you measuring performance?  Can you post logs?

Regards

James

Hi James,

Thank you for your reply.

JJD said:

How are you measuring performance?  Can you post logs?

Please refer to the thread below for information on how to measure performance.
(+) AUDIO-AM62D-EVM: Difference in execution clock cycles between AM62D and AM62A, and C7x - Processors forum - Processors - TI E2E support forums

I created a separate thread because I wanted to confirm whether there were any differences from the perspective of DDR.
Based on your answer, I assume there is a high chance that there are no differences in DDR.

Best regards,
O.H

Ok, thanks.  I agree that the performance difference doesn't appear to be related to DDR.  

Regards,

James

Thanks. I will consult with you if additional questions arise

Best regards,
O.H