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DDR3 interface without termination resistors?

Robert F.
Intellectual 855 points

Hello,

Can the termination resistors be removed if following topology is used?

4 Memory chips:

2 chips for DDR0 (same PCB position, one chip on the TOP, one chip on the BOTTOM)
- one chip for DDR0 Data 0-15;
- second chip for DDR0 Data 16-31;
- DDR0 Control / Command / Clocks connected by T branch just under the memory chips

2 chips for DDR1 (same PCB position, one chip on the TOP, one chip on the BOTTOM)
- one chip for DDR1 Data 0-15;
- second chip for DDR1 Data 16-31;
- DDR1 Control / Command / Clocks connected by T branch just under the memory chips

This topology is supported by Freescale chips for DDR3 - Is it supported by C6A816x too?  

Thank you,

- Robert

  • 0
    TI__Mastermind 25055 points

    Robert,

    If part or all of one of the interfaces is not used, then pins can be left unterminated.  The DDR3 Layout Specifications section of the datasheet describes the termination requirements for all supported configurations.

    Regards,
    Marc

  • 0 in reply to MarcPyne
    Intellectual 855 points

    Hi Marc,

    thank you for your answer. I am planning to use both DDR3 channels (DDR0 and DDR1).

    I have seen the termination requirements in datasheet, but I was curious. (For example Datasheets says to use termination resistors even for one DDR3 device.)

    My intention is to use something like ADDR_CTRL Routing for Two Mirrored DDR3 Devices (see the picture from datasheet) ... and I thought, that could work even without the termination resistors (?).

    ... or have a look on my current C6A816x layout at this video were I would like to remove the termination resistors:
    http://www.fedevel.com/welldoneblog/2011/07/altium-designer-ddr3-routing-and-pcb-layout-video/

    I know the safest aswer is: "Use termination resistors" (I would use this answer if someone ask me this question), but if possible, I really would like to know what your engineers think about that.

    Thank you,

    - Robert

  • 0 in reply to Robert F.
    TI__Intellectual 1670 points

    Using termination resistors is the safe answer, as you mention, so I would recommend keeping them.  They are a problem as well as a solution though, since they do complicate the routing.

    Knowing whether a design will work without resistors is really only possible with simulations that have been correlated to the real world, and since I don't have that luxury with your design, I can only suggest to follow the guidelines.  They also serve to help with EMI if there is a failing test that might require tweaking the DDR interface.

    I have seen designs work without termination resistors, but on OMAP, not on DaVinci devices (and only on DDR2).  DaVinci devices use stronger buffers that require more termination than the weaker OMAP buffers.  If you do choose not to use termination resistors, I would keep the traces as short as possible, while following the guidelines for skew, etc.  I don't know if any customers who have tried operating a Davinci device without the resistors on DDR3.  Of course you could replace them with 0 ohm resistors once you are done, and eliminate them in the next design if the prototype was tested over temperature, voltage, and process variations with this setup.

    Of course, not using resistors as we recommend in the DDR layout guidelines means you will be operating the device outside of the device spec, so we would never recommend this.

    I hope that helps!

    Keven

  • 0 in reply to MarcPyne
    Prodigy 110 points

    Hi,Marc

    I encounter the nand read speed issue during my development, the detail procedure as below:

    1.I used the Micron Large page x16 NAND for development.

    2.In \u-boot-2010.06-psp04.00.00.10\arch\arm\include\asm\arch-ti81xx\Mem.h file , I modified the M_NAND_GPMC_CONFIG5 bit 0-4(which means RDCYCLETIME). from 1e(default) to 07(fast speed as calculated) .

    3.I print the value of M_NAND_GPMC_CONFIG5 ,lt's vaule changed as i modified.

    4. I through Oscilloscope I observed  between both setting(1e and 07) TOE(which means read cycle time) are around 632 ns.looks like the change doesn't take the effect for the hardware.

    any one encounter the same issue? whether any other setting i need to do to solve this issue?