DM814x : termination resistors for DDR3

Hi Tamir,

tamir harush said:

can you please point the place in the DM814x data sheet that mention the value of the end termination resistors for the addresses, controls and clocks?

Please see Table 8-69. PCB Stackup Specifications, line 13:

Single-ended impedance, Zo    min 50 ohm     max 75 ohm

In the DM8148 EVM, which is used as a reference schematic for DM814x based board, these Z0 termination resistors have the value of 51ohm.


See also the below e2e thread:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/193508.aspx

Best regards,
Pavel

Hi,

please see JEDEC standard below - the value of the end termination resistor Rtt is 36 Ohms..

why doens't the standard matches TI's suggestion regarding the value for the control & addresses end termination?

Note - the standard recommened 36 Ohms regardless the value of the trace controlled impedance.

2555.JEDEC standard.docx

thanks 

Tamir,

Rtt (DDR address and control terminator) is defined in the DM814x datasheet:

min value: Z0 - 5 (45ohm)

typical value: Z0 (50ohm)

max value: Z0 + 5 (55ohm)

tamir harush said:

please see JEDEC standard below

Is this the JEDEC DDR3 SDRAM standard, JESD79-3F?

Best regards,
Pavel

Hi Pavel,

the attachmenet was taken from JEDEC standard No. 21C (unbuffered SO-DIMM reference design specification).

We are facing difficulties with the DDR’s interface in the TMS320DM814x DSP.

The speed performance is low, if comparing to 6424 DSP that works with DDR2 and in a much lower frequencies –

Its speed performance is 2 times faster than the 814x.

I’m attaching a table from the same standard documentation regarding signal matching.

Can a trace matching (between traces inside a Byte lane) that exceeds the standard cause this performance downgrade?

Thanks!

3487.JEDEC standard matching.docx

Tamir,

Please refer to the below E2E threads for DSP performance:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/319115.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/278391.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/308389.aspx

Regards,
Pavel

Hi Pavel,

Tamir, is working in my Team, and I would like to further investigate this issue.

In one of the links you have attached to your previous post, there are some indications that there was a silicon issue regarding the DDR3 interface.

Can you please elaborate on this silicon issue?

Our silicon revision is PG3.0, did TI ever encounter DDR3 performance issues in regard to this silicon version specifically?

Hi Avi,

The differences between PG3.0 device and previous versions are described in the device Silicon errata.

Avi Elbaz said:

In one of the links you have attached to your previous post, there are some indications that there was a silicon issue regarding the DDR3 interface.

Can you please elaborate on this silicon issue?

The differences between 3.0 and 2.1 are provided in Table 6. Silicon Revision 2.1 Advisory List

The advisory related to the DDR3 bandwidth is:
Advisory 2.1.68 — DDR DMM: Continuous Writes From Cortex-A8 Occasionally Starve Other Requestors for DDR Bandwidth

This errata is valid for 2.1 and fixed for 3.0.

Avi Elbaz said:

Our silicon revision is PG3.0, did TI ever encounter DDR3 performance issues in regard to this silicon version specifically?

I do not think we have errata specific for PG3.0. All advisories valid for 3.0 are also valid for previous versions.

Best regards,
Pavel

Pavel, our DDR3 interface is NOT used by the ARM, but the DSP only (ARM is disabled). I'm not sure I follow your reference to a Cortex-DDR issue in the 2.1 advisory.

Do you, or don't you have a silicon related issue regarding the DSP and DDR3 interface in silicon version 3.0??        (I already went through sections 2.1.1, 2.1.2 and 2.1.3 is sprz343c)

Thanks.

Avi,

Avi Elbaz said:

Pavel, our DDR3 interface is NOT used by the ARM, but the DSP only (ARM is disabled). I'm not sure I follow your reference to a Cortex-DDR issue in the 2.1 advisory.

As you are with PG3.0, then this errata is NOT valid for you (may be I was not clear enough in my previous post).

Avi Elbaz said:

Do you, or don't you have a silicon related issue regarding the DSP and DDR3 interface in silicon version 3.0??

No, there are no silicon issues regarding the DSP and DDR3 interface in PG3.0 device.

But I can see these 3.0 usage notes:

2.1.1 DDR3: JEDEC Compliance for Maximum Self-Refresh Command Limit

2.1.3 DDR2 and DDR3 Requires Software Leveling

Best Regards,
Pavel

Like I said, I already went through sections 2.1.1, 2.1.2 and 2.1.3 is sprz343c !

Now, regarding the DM8148 EVB (designed for TI by Mistral):

In one of his previous posts, Tamir was referring to a case in which the length matching of DQ/DQS within a Byte lane exceeds the SO-DIMM JEDEC requirement (was attached in his post). He was talking about exceeding this requirement by a factor of 20 !!

Can this situation cause a significant degradation in performance?

Avi,

I am checking this with the DDR HW experts.

Meanwhile, in the below post is attached the DDR3 JEDEC specification (JESD79-3E) which should be used for DM814x device. Is this the same JEDEC specification that you are using/referring to?

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/276961/974311.aspx#974311

Regards,
Pavel

Thanks, I'll be waiting for the inputs from your DDR3 experts.

As for the JEDEC I was referring to, it's attached here.

1263.JEDEC_SODIMM_DDR3_4_20_18R18A.pdf

The way the DDR3 is deployed on the DM8148 EVB by Mistral, you could refer to it as type "C" in this JEDEC.

Avi,

SO-DIMM DDR is not supported for DM814x device. Only the DDR devices described in the DM814x datasheet are supported. See the below links for more info:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/193308.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/71797.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/136728.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/102387.aspx

Best regards,
Pavel

Pavel,

I didn't mean an actual physical SO-DIMM..... I meant that the DDR3 devices on the EVB are deployed as if it is a DIMM type "C" from the JEDEC.

As such, you should follow the JEDEC recommendations, also regarding trace termination on board !

The Mistral EVB doesn't do that.

Once again, could it be the reason for such performance degradation we experience?