AM6442: Request a Schematic Review

Hello Kiyoshi Kogure

Thank you for the query.

Please send a private message.

Regards,

Sreenivasa

Hello Kiyoshi Kogure

Thank you for the schematics review request. 

I shared the schematics with comments over private chat.

In addition to the review comments, please note the below.

Based on your request to prioritize the schematics review I have prioritized the schematics review.
Please refer attached PDF schematics with comments embedded.
Please let me know if you have any comments, suggestion, customer inputs or queries.

The comments are categorized as below
Observations/Notes: Indicates the coverage or observations, suggest customer reviews this once
Suggestions: These are good to make changes that customer can decide
Update: Recommend making the updates unless customer is sure that these changes are not required

The recommendation is to start a E2E for generic queries that does not include customer specific information.

General Notes (For customer to review)

General Notes (For customer to review)

• SOC or processor - means the sitara processor used in the design
• Attached device - means DDR or flash memory, communication interface, sensors or other external devices interfaced to the processor
• We have reviewed the schematics to the best. Since the implementation and design flow is customer specific, there may be similar updates that customer will have to review and make the updates.
• Verify all the core, analog and IO supplies for the SOC are connected to the recommended supply voltage levels
• Verify all the peripheral core, analog and IO supplies for the SOC are connected through ferrite filter
• Ensure all the pullups connected to the SOC are pulled up to the correct I/O voltage (matches with the IO supply referenced for the specific IO groups)
• Verify the device selection section of the data sheet based on the requirement to confirm the device selection
• Verify the pin configuration for the memory interface, communication and IO interfaces using the sysconfig - pinmux tool
• Verify the mapping of the schematics symbol pin number and name with the pin name and number as per the pin attributes section of the data sheet
• Any SoC pad that has a trace connected and not being actively driven needs an external parallel pull
• Verify Device specific Errata for allowed bootmode configuration and erratas affecting the functionality
• Verify Pin connectivity table of the data sheet for connecting any unused pins or peripherals including supplies
• Please read through the SOC data sheet pin connectivity requirements and ensure the recommendations are followed
• When Adjustable DC/DC or LDO are used, verify the resistor divider ration matches the required output voltage
• Resistor divider tolerance for discrete DC/DC or LDO output supply feedback is 1% for improved output accuracy
• Note the I2C interface exceptions and pin connectivity requirements
• Add provision to isolate and probe the OBSCLK for testing
• Recommendation is to always perform simulations on the custom board
• The system designer must use the IBIS model of each device connected to a signal and the PCB signal trace extractions in a simulation environment to determine the rise/fall time of any signal being sourced by AM62x or other processors 3T caps are used to optimize the use of caps and optimize the PCB look inductance.

Notes related to i2C and SPI

• Open-drain output type I2C interface - a pullup is required irrespective of IO usage or configuration
• Open-drain output type I2C interface - does not support high speed when the IO supply and the I2C signals are connected to 3.3V
• Connecting 3.3V to IO supply group and connecting 1.8V supply to IO is not allowed
• SPIx_CLK a series resistor recommended irrespective of IO configuration
• SPIx_CLK add a pull down for the clock input near to the attached device clock input

Notes on software SDK version

• In case the project is a new platform, please ensure the latest SDK is used.
• In case the project is a derived project using older revision, the recommendation is to review the changes (release notes) with respect to the version used vs latest. Based on the changes observes, the required discretion (approach) could be followed - Example updating any of the drivers of interest (Reach out to the TI applications team through E2E)

Common SOC LVCMOS IO interface guidelines (For customers to review and make updates)
1. Most of the SOC IOs are not fail-safe. No external input is recommended to be applied before the processor supply ramps
2. SOC LVCOMOS IOs have slew rate requirements specified, applying a slow ramp input or connecting a cap at the input is not recommended
3. Connecting a cap load >22pF at the LVCMOS IO output is not recommended. DNI cap or perform simulations based on the use case.
4. SOC IO buffers are off during Reset. A pull is required near to the attached device being driven by the SOC IO that could float
5. Any SOC IO that has a trace connected needs a parallel pull. When adding pull is not feasible, ensure the traces are routed away from noisy signals
6. Connecting processor IOs that can be configured for alternate function, directly to supply or ground is not allowed or recommended (including boot mode inputs). Custom board can have an configuration issue with the firmware and mis-configures these LVCMOS GPIOs that were intended to be inputs, to be outputs driven logic high instead.
7.Verify cap loading of the SOC output (when any cap value >22 pF (use case dependent, max value) is connected, recommendation is to simulate), slew rate of the input signal (LVCMOS input slew should be 1000 ns or less), IO compatibility and fail-safe operation between the SOC IOs and attached devices
8. Ensure ST_EN bit in the PADconfig register is enabled for all the IOs

Recommended References for review and design of custom board
AM64x
Data sheet
AM64x Sitara Processors datasheet
www.ti.com/.../sprsp56

AM64x /AM243x
Processors SiliconAM64x /AM243x Processors Silicon Revision 2.0Texas Instruments Families of Products Technical Reference Manual spruim2h
www.ti.com/.../spruim2

Hardware Design Guide
www.ti.com/.../sprad67
Hardware Design Considerations for Custom Board Using AM6442, AM6422, AM6412 and AM2434 (ALV, ALX) Processor (Rev. D)
Schematic Design and Review Checklist for AM64x
www.ti.com/.../spracu5
AM6442 , AM6422 , AM6412 and AM2434 Processor Schematic Design Guidelines and Schematic Review Checklist (Rev. E)
AM64x\AM243x DDR Board Design and Layout Guidelines
www.ti.com/.../spracu1
AM62x, AM62Lx DDR Board Design and Layout Guidelines
www.ti.com/.../sprad06
Errata
www.ti.com/.../sprz457

PRU-ICSSG
www.ti.com/.../sprac90g.pdf

Schematic review request (internal)
e2e.ti.com/.../4661966
AM64x Schematic checklist
e2e.ti.com/.../faq-am625-am623-am62a-am62p-am62d-q1-am64x-am243x-design-recommendations-custom-board-hardware-design---schematics-review-checklists

AM64x Schematic self-review
e2e.ti.com/.../faq-am6442-am6441-am6422-am6421-am6412-am6411-am243x-design-recommendations-custom-board-hardware-design---custom-board-schematics-self-review
e2e.ti.com/.../faq-am625-am623-am62a-design-recommendations-commonly-observed-errors-during-custom-board-hardware-design-sk-schematics-updates-for-design-update-note
e2e.ti.com/.../faq-am625-am625-am623-am62a-am62p-am62d-q1-am64x-am243x-design-recommendations-custom-board-hardware-design---list-of-errors-observed-during-customer-schematics-review
e2e.ti.com/.../faq-am625-am623-am62a-am62p-am62d-q1-am64x-am243x-design-recommendations-custom-board-hardware-design---queries-related-to-soc-data-sheet-pin-attributes

Design notes
e2e.ti.com/.../faq-am6442-am6441-am6422-am6421-am6412-am6411-custom-board-hardware-design---design-and-review-notes-for-reuse-of-tmds64evm-schematics
e2e.ti.com/.../faq-am6442-am6441-am6422-am6421-am6412-am6411-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am64b-schematics

Frequently Asked Questions FAQs
e2e.ti.com/.../faq-custom-board-hardware-design---master-complete-list-of-faqs-for-all-sitara-processor-am62x-am64x-am243x-am335x-families
e2e.ti.com/.../faq-am6442-am6441-am6422-am6421-am6412-am6411-custom-board-hardware-design---faqs-related-to-processor-collaterals-functioning-peripherals-interface-and-evm-starter-kit
e2e.ti.com/.../faq-am62x-am64x-custom-board-hardware-design-how-to-handle-used-unused-pins-peripherals-e-g-gpios-serdes-usb-csi-mmc-emmc-sd-card-csi-oldi-dsi

www.ti.com/.../TMDS64EVM
www.ti.com/.../SK-AM64B

Downloadable design files on TI.com list for SK/EVM
TMDS64EVM Design Package Folder and Files List
www.ti.com/.../sprt782
ZIP file
www.ti.com/.../sprr462
SK-AM64B Design Package Folder and Files List
www.ti.com/.../sprt783
ZIP file
www.ti.com/.../sprr460

Regards,

Sreenivasa

Hello Kiyoshi Kogure

I have shared the schematics with review and general guidelines as above.

Please review and let me know your thoughts or if you have any queries.

Regards,

Sreenivasa

Hello Kiyoshi Kogure

We have an excel that lists all the SOC supply pin and also includes the connection information on the EVM or SK.

Please ensure you review the custom design for the power pins mapping and connections before board build.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1595775/faq-am625-am623-am620-q1-am62l-am62a-am62p-am62d-q1-am64x-

am243x-custom-board-hardware-design---processor-pin-mapping-and-sk-board-connections-supply-rail-capacitors-and-ferrites 

Regards,

Sreenivasa

Dear　TI  Expert Engineer.

Thanks for providing more information

We will review this information and proceed with the design.

Regards,