Part Number: AM6442
I am working on an application where I need the PRU to read DRAM0 but I need to know exactly how many cycles the LBBO instruction takes; every time no matter what.
In order to do this, I need to make sure if any other cores are writing to DRAM0, that the PRU always wins arbitration so the number of clock cycles stays constant.
From this E2E post, the PRU engineer mentions a way to make sure the PRU wins arbitration every time it tries to read DRAM0.
"If you want to completely avoid arbitration delay, you could program the non-PRU core to perform multiple 4 Byte writes instead of a single long write. In that case, the PRU would win arbitration every clock cycle it initiates a read. "
From my understanding, if the R5F is writing to DRAM using the following API, then because each individual write is < 4bytes, whenever the PRU tries to read DRAM, it will win arbitration.
I understand winning arbitration means the R5F will pause during the four-byte write, and PRU will read the memory, then R5F will finish writing the remaing bytes from the write call?
R5F API Call: HW_WR_REG16(0x30000000 + OFFSET, VALUE);
