AM62A7-Q1: DSS: Lower emissions when using 10 bit video output

Bas Vermeulen

Part Number: AM62A7-Q1
Other Parts Discussed in Thread: AM62P

Hi,

For one of our products we are using the DSS to output video. This causes some EMI interference in a specific bandwidth that we would like to lower. We are using BT.656 mode on a 10 bit data bus.

We wanted to try doing this by lowering the drive strength on the VOUT0_DATA0-9 and VOUT0_PCLK pins.

We have some questions regarding this:

The drive strength parameter for the pinmux is set as 0 (default). The other values (1-3) are set as reserved. Is it possible/allowed to set these to 1-3, and what drive strength is then used?
Is there another way to configure the DSS to output less energy on the output pins?
Is it possible to use spread spectrum for clock and data lines? If so, how do I configure this? And is this compatible with bt.656 mode?

Any help regarding this would be greatly appreciated.

Regards,

Bas Vermeulen

3 months ago

0 Stanislav Stilyanov 3 months ago

TI__Mastermind 25080 points

Hello Bas Vermeulen,

Answers below.

1. Please refer to the latest TRM, Table 14-11106. Description Of The Pad Configuration Register Bits

Only Fast is the other supported option.

2. Not internally. You may need to revisit the board design. There are several e2e FAQs, app notes and other collaterals from TI to support board design. Actually note that the energy is not coming from DSS directly but from shared (multiplexed) LVCMOS Tx buffers behind pins. All options are those listed in PADCONFIG registers.

3. You can refer to this thread for how to enable SSC. AM62A7: AM62A7: Configuring Spread Spectrum Clocking on DPI You may want to search for 'spread' in the browser to skip some other topics discussed inside.

Let me know if you want me to search for PCB design guidance collaterals.

Best Regards,

Stan

0 Luis Parga 3 months ago in reply to Stanislav Stilyanov

TI__Intellectual 1320 points

Hi Bas Vermeulen,

Is this for a DPI application? If so, please refer to below application note.

https://www.ti.com/lit/pdf/spradk1?keyMatch=AM62P%20spread%20spectrum%20clocking&tisearch=universal_search

Best regards,

Luis Parga

0 Bas Vermeulen 3 months ago in reply to Stanislav Stilyanov

Intellectual 1000 points

Hi Stanislav Stilyanov ,

Could you search for PCB design guidance collaterals for us? That would be much appreciated. We'll try the drive strength and SSC in parallel.

Regards,

Bas Vermeulen

0 Bas Vermeulen 3 months ago in reply to Luis Parga

Intellectual 1000 points

Hi Luis Parga

We are connecting an SMPTE serializer to the video output pins. We are using BT.656 mode, with 10 bits output.

Do you have a patch for the spread spectrum interface that is being talked about in the document you linked?

I could integrate that into our (AM62A 11.1 SDK) kernel more easily.

Regards,

Bas Vermeulen

0 Bas Vermeulen 3 months ago in reply to Bas Vermeulen

Intellectual 1000 points

Divyansh Mittal ,

In AM62A7: AM62A7: Configuring Spread Spectrum Clocking on DPI you offered to share the patches/modifications needed to allow spread spectrum DPI clocks for SDK 10, would it be possible to get those changes as well for SDK 11.1?

Regards,

Bas Vermeulen

0 Divyansh Mittal 3 months ago in reply to Bas Vermeulen

TI__Genius 15980 points

Hi Bas,
Due to huge number of commits, it is going to be difficult to provide the patches for 10.1. We are checking internally if it will be feasible for 11.01, though this support would be there in the next release for AM62A. The next release for AM62A will take time (could be around Dec, 2026).

0 Bas Vermeulen 3 months ago in reply to Divyansh Mittal

Intellectual 1000 points

Hi Divyansh Mittal ,

If you have the changes needed on the DM R5 side, I can try to get things working with kernel 6.12.x (11.2.13 seems to have all the required patches for the kernel side changes). I would need to make sure that nothing added between 11.1 and 11.2 interferes with our requirements.

Regards,

Bas Vermeulen

0 Bas Vermeulen 3 months ago in reply to Bas Vermeulen

Intellectual 1000 points

Hi Divyansh Mittal ,

If I want to implement spread spectrum for PLL17 (only) in the firmware, what would be the correct place to do this? I have access to the firmware builder, and can make changes there if needed.

We only need to enable spread spectrum for DPI, it doesn't have to be configurable. The tests we did with enabling it in userspace yielded positive results, now I need to make it permanent in a stable way.

Regards,

Bas Vermeulen

0 Bas Vermeulen 3 months ago in reply to Bas Vermeulen

Intellectual 1000 points

Hi Divyansh Mittal ,

I think I have this implemented in the DM R5 firmware, would it be possible to review my changes?

From 1a3c6255001faab0f124cc8f48377e9b4b3dc574 Mon Sep 17 00:00:00 2001
From: Bas Vermeulen <sebastiaan.vermeulen@bench.com>
Date: Wed, 22 Apr 2026 17:14:15 +0200
Subject: [PATCH] clk_pll_16fft: Enable spread spectrum for PLL17

---
 .../pm/drivers/clock/clk_pll_16fft.c          | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/source/drivers/device_manager/rm_pm_hal/rm_pm_hal_src/pm/drivers/clock/clk_pll_16fft.c b/source/drivers/device_manager/rm_pm_hal/rm_pm_hal_src/pm/drivers/clock/clk_pll_16fft.c
index 84ae963..ae27fc9 100644
--- a/source/drivers/device_manager/rm_pm_hal/rm_pm_hal_src/pm/drivers/clock/clk_pll_16fft.c
+++ b/source/drivers/device_manager/rm_pm_hal/rm_pm_hal_src/pm/drivers/clock/clk_pll_16fft.c
@@ -699,6 +699,28 @@ static sbool clk_pll_16fft_program_freq(struct clk			*pll_clk,
 		ctrl |= PLL_16FFT_CTRL_DAC_EN;
 	}
 
+	/* Enable Spread Spectrum for PLL17 */
+	if (pll->idx == 17) {
+		u32 ss_ctrl   = 0x00000000;
+		u32 ss_spread = 0x0006000a;
+
+		if (ret) {
+			err = pm_writel_verified(ss_ctrl, (u32) pll->base + (u32) PLL_16FFT_SS_CTRL(pll->idx));
+			if (err != SUCCESS) {
+				ret = SFALSE;
+			}
+		}
+		if (ret) {
+			err = pm_writel_verified(ss_spread, (u32) pll->base + (u32) PLL_16FFT_SS_SPREAD(pll->idx));
+			if (err != SUCCESS) {
+				ret = SFALSE;
+			}
+		}
+
+		ctrl |= PLL_16FFT_CTRL_DSM_EN;
+		ctrl |= PLL_16FFT_CTRL_DAC_EN;
+	}
+
 	if (ret) {
 		err = pm_writel_verified(freq_ctrl0, (u32) pll->base + (u32) PLL_16FFT_FREQ_CTRL0(pll->idx));
 		if (err != SUCCESS) {
-- 
2.43.0

NOTE: Patch modified as there was an error in line 36 and 37 (!= instead of |=).

Regards,

Bas Vermeulen

0 Stanislav Stilyanov 3 months ago in reply to Bas Vermeulen

TI__Mastermind 25080 points

Hi Hi Bas Vermeulen,

You can start with this FAQ:

(+) [FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP Custom board hardware design – Display Parallel Interface (DPI) 24-bit RGB- display interface - Processors forum - Processors - TI E2E support forums

Thanks,

Stan

0 Divyansh Mittal 3 months ago in reply to Stanislav Stilyanov

TI__Genius 15980 points

Hi Bas,
There are multiple changes that would be needed on the DM R5 side as well, our expert is currently evaluating on how to backport the patches to 11.01. Please allow some time for the expert to respond.

0 Bas Vermeulen 3 months ago in reply to Divyansh Mittal

Intellectual 1000 points

Hi Divyansh Mittal

Sure, that's fine. In the mean time, would it be possible to review the patch I made? It works, in that the registers are set to the values I expect to read, I would just like to know that the place/manner of setting the registers is correct.

This does not include the whole device tree interface, it just sets spread spectrum for PLL17 to a fixed value when changing the frequency.

Regards,

Bas Vermeulen

0 Anastas Yordanov 3 months ago in reply to Bas Vermeulen

TI__Genius 13280 points

Hello Bas Vermeulen,

Please expect that some delay in the response by Divyansh is possible (earliest today COB).

Thanks for your patience !

Best Regards

Anastas Yordanov

0 Meet Thakar 3 months ago in reply to Anastas Yordanov

TI__Mastermind 22855 points

Hi Bas,

We don't recommend direct register writes to configure this, we are still working on testing the patches (to back port changes from 11.2 to 11.1) we recommend you wait for that.

Best Regards,

Meet.

0 Bas Vermeulen 2 months ago in reply to Meet Thakar

Intellectual 1000 points

Hi Meet Thakar

Understood. If you look at the patch I propose to use, it modifies the DM firmware to write the registers when the PLL is disabled. I just want to make sure that this is the correct place to do it.

I will use the patches you are working on when those are available, but since I need a solution now, this is what I have.

If it is possible to review the patch I provided, that would be much appreciated.

Bas Vermeulen

0 Borislav Lazarkov 2 months ago in reply to Bas Vermeulen

TI__Intellectual 1650 points

Hello Bas Vermeulen,

Please expect that some delay in the response by Meet Thakar is possible.

Thanks for your patience !

Best Regards,

Borislav Lazarkov

0 Luis Parga 2 months ago in reply to Borislav Lazarkov

TI__Intellectual 1320 points

Hi Bas,

In general, this SSC implementation sequence needs to be done after the full PLL sequence has happened and the PLL has been already locked. So, while the official patch from Meet is being worked internally, I suggest you modify your patch to comply with the note above for your testing purposes.

Best regards,

Luis Parga

+1 Jay Goyal 2 months ago in reply to Luis Parga

TI__Expert 3530 points

Hi Bas,

Apologies for the delay in the reply. For enabling the feature on AM62A, you will need to rebuild the DM R5 application, which requires access to firmware builder[1]. This requires an active NDA with TI to get access. I am sharing patches on top of the Linux kernel and Firmware Builder to enable SSC.

On top of these changes, you also need to configure SSC using the parameters using device tree overlays as mentioned in this document for AM62P[2]. Do note that instead of &dss0, it is &dss for AM62A.

Regards,
Jay

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/6355.kernel.patch
https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/6355.firmware_2D00_builder.patch

[1] https://www.ti.com/drr/opn/FIRMWARE-BUILDER-AM62A
[2] https://software-dl.ti.com/processor-sdk-linux/esd/AM62PX/latest/exports/docs/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.html

0 Bas Vermeulen 2 months ago in reply to Jay Goyal

Intellectual 1000 points

Hi Jay Goyal ,

The patches work, but only if the frequency is fractional. If the frequency is an integer division like we had with our 27 MHz frequency, it doesn't enable the spread spectrum (because DSM_EN and DAC_EN are not enabled if that's the case).

We worked around it by lowering the frequency slightly, but this might throw some people a nasty surprise if they are not aware of it.

If you get a fix for this, could you send me the patch?

Regards,

Bas Vermeulen

0 Luis Parga 2 months ago in reply to Bas Vermeulen

TI__Intellectual 1320 points

Hi Bas,

Spread spectrum clocking is not supported when integer divide mode is used. This is only supported when using fractional mode. Please accommodate accordingly.

Best regards,

Luis Parga