The glitch occurs on I2C0 SDA of DM8168

Omin Chou

Dear all,

I measure the I2C waveform on DM8168EVM(rev C). It occurs the glitch on I2C0 SDA. Please refer the below waveform. Can anyone provide me the solution to eliminate it?

Thanks in advance.

B.R.

over 12 years ago

0 Steve Clynes over 12 years ago

TI__Mastermind 43875 points

This is not a glitch per se. It is simple the bus being released at the end of the cycle and is allowed as per the I2C spec as long as it does not occur whilst CLK is high.

It is difficult to see from the capture, but this might simply be the ACK period, where it would be the responsibility of the slave device to hold data low for the ACK cycle. If there is no slave device responding to the message then it would also cause SDA to go high.

BR,

Steve

0 Omin Chou over 12 years ago in reply to Steve Clynes

Genius 3555 points

Dear Steve,

Thanks for your clarification on this concern. It's clear for me now.

B.R.

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The glitch occurs on I2C0 SDA of DM8168