AM35xx LPDDR tuning (empirical)?

We're seeing varying results on our AM3505 design prototype yields. Some powerup fine and run reliably while others crash at varying points in U-Boot, Kernel load, or minutes / hours after booting Android. We suspect the LPDDR layout or settings are non-optimal.

We've read the TRM, DS, and Wiki notes; have included the external strobe loop matched to CLK + ave DQS, yet setting the strobe for "internal" appears to give better results.

Whats missing is an explanation of how the processor DDR interface samples data. With this explanation one could empirically tune and debug these issues (e.g. what should the STRBEN input and DQ signal phase be at the processor for an optimal eye?)

1. Is there a description of how the DDR interface samples read data? and are there any "tunable" elements in the interface? (e.g. delay lines for making phase adjustments for inbound data)

2. I've been unable to find AC parameters for the interface - do these exist? It appears TI's stance is copy the layout guideline we provide exactly and everything will work. This leaves the user adjusting LPDDR drive strength and perhaps AM35xx termination Z and trying to evaluate stability. And if the interface doesn't work, information that would help with debug are missing.

Thanks ... Jim