Good morning.
My name is Alberto Lombardi, working in the company of SELEX Florence and I am testing.
Working with Agilent 3070 machine, and I developed a fixture for testing a card that features a
OMAP DM3730 houses CBPA (515 pins PBGA) and a TPS65950.
I have withdrawn from the site TEXAS BSDL models of the two components, and tried to perform the first operation that usually do ATE machines, through JTAG or disabling of individual components on and in order to be able to run the boundary scan test of each component having others with their outputs in the state of disable.
Here are start my problems, 'cause the two components, do not enter the mode' boundary scan.
Then I started testing different, ie:
for OMAP DM3730:
I covered the BSDL model, but inside it did not describe any COMPLIANCE.
I watched the various components of the datasheet, but I have not found any news about it.
I joined the forum, from which I am writing and I found this document:
http://processors.wiki.ti.com/index.php/Boundary_Scan_on_OMAP35x
I performed the procedure, described in this document, but I believe that this procedure allows access to the boundary scan module Manages icepick, but then what is needed to run the model BSDL downloaded from TEXAS also the steps, he steps some 'curious, for example, is said to drive the signals to EMU1 EMU0 and pullups, when in the datasheet, it is described that the signals EMU0 EMU1 and should be the default with pullup resistors.
Other strange thing and the IDCODE, which is described here and in the file BSDL and not 'shown, although in this procedure is reported.
Another strange thing, and the selection signal SYS_NRESPWRON, and the layout of my card and 'an output signal from the TPS, and then' generated by the component and I clearly cannot influence.
And 'possible to have documentation on the module Manages icepick?
What version of icepick and 'contained in the DM3730?
As for the TPS65950 I performed the following tests:
I covered the BSDL model, but inside it did not describe any COMPLIANCE.
I watched the various components of the datasheet, but I have not found any news about it.
I joined the forum, from which I am writing and I found this document:
TPS65950: How to use JTAG for boundary scan
- I followed the steps above decrypts, but I could not get in the mode 'of the boundary scan tps65950.
With regard to the document I have some things to ask:
Test the signal, it should be directly connected to 1.8V, for the JTAG available, or requires a resistor in series? If so, what value should have this resistance?
TEST RESET signal, in which logic state is stored for access to the JTAG boundary scan test and run the disable the component?
In summary, I ask you, please, to show me the information necessary to condition the two components in order to gain access and perform JTAG boundary scan testing of each component.
I have to try a first batch of 1000 cards, and I would like a response in a reasonable time, or a suggestion on how to test these cards, using tools of TEXAS, for example, which are not aware, I submit that must be reliable procedures for manufacturing test.
Greetings
Alberto Lombardi