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am335x mcasp as the i2s master and codec as the slave

king liu
Prodigy 150 points
Other Parts Discussed in Thread: TAS5716

dear all

Now I want to port a new codec driver  tas5716 to am335x ics platform .

As the tas5716 can only as the slave ,i change the am335x mcasp as the maser .

#define AUDIO_FORMAT (SND_SOC_DAIFMT_DSP_B | \
                SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF)

to 

#define AUDIO_FORMAT (SND_SOC_DAIFMT_DSP_B | \
                SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_IB_NF)

now the i2s BCLK(mcasp_aclkx) alwalys is 24mhz,the WCLK(mcasp_fsx) is 750khz,

the codec can  not work,have no audo.

Anybody know how to change to BCLK(mcasp_aclkx)?

  • 0
    Prodigy 150 points

    dear all

    The Mclk of am335x is 24Mhz, and I chage the regsite DAVINCI_MCASP_ACLKXCTL_REG 0xb0 the bit4-0 to F ,

    Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX.  Divide-by-15 .

    And the sample clk = 24Mhz/16/32 = 46.8khz , the pll div can not div to 48khz or 44.1khz.

    Can anybody give me some suggestions about how to set the div to reduce the sample clk to 44.1k or 48khz?

  • 0 in reply to king liu
    TI__Expert 4440 points

    Hi King,

      As you're using the master mode, you need to generate the clock from the main OSC, according to the TRM. If you want to change the aclk, you can refer to the ACLKXCTL register CLKXDIV.

      It seems that you want to get the clk frequence 48khz. the sample clk =24Mhz/16/32=24*1024khz/16/32=48khz. So is the 48khz clock is proper for your application? If it is, maybe you need to check other parts of your design.

    Best Regards.

    Steven. 

     

  • 0 in reply to Steven Liu1
    Prodigy 150 points

    dear Steven

    Are you sure the 24Mhz=24*1024khz in am335x？

    I think the 24Mhz=24*1000khz。And i have do the experiment ,the main osc is 24mhz，i set the clkdiv 0xf。

    And measure the  sample clk = 24mhz/16/32=24*1000/16/32=46.8khz by using the oscilloscope.

  • 0 in reply to king liu
    TI__Expert 4440 points

    Hi King,

      Sorry for giving you the wong information. Yes, that's right. Have you seen the TRM about McASP? the mcaclk is divided from AHCLK, and AHCLK is divided from the main osc 24MHz. which meas : mcaclk= 24MHz/D1/D2, D1, D2 is determined by AHCLKRCTL.HCLKRDIV and ACLKRCTL.CLKRDIV. If you want to get the 48 kHz, just make D1*D2 =500 is OK. right? Another thing needs your attention is that which clock you chooe to connect to the mclk of the codec chip. That's related to the D1.

    Steven. 

  • 0 in reply to Steven Liu1
    Intellectual 595 points

    Hello King,

    you will not be able to use the am335x as I2S Master, because you cannot generate the I2S clock from the available clock domain (MAIN_OSC) to achieve a I2S Frame of 44.1KHz or 48.0 KHz. Both clock dividers CLKRDIV and AHCLKRDIV are integer dividers and cannot divide down to a multiple of 44.1 or 48.0 ! You might need to feed a multiple of 44.1 or 48.0 KHz into the AHCLKR pin and the divide it down to the wanted frequency. So basically the am335x will stay in slave mode and only generate the I2S Frame signal. For more details, please consult the spruh73g.pdf page 3751 ff and in special the chapter 22.3.5.2 Receive clock.

    Example: AHCLKR = 3.072MHz HCLKRDIV = 0 -> ACLKR = 3.072MHz               32bit/sample * 2audio slots (L+R) *48kHz (sample rate) = 3.072MHz

    Klaus

    PS: please be aware, that there´is a bug in the manual Figure 22-18 -> divider names/locations are switched !!!!!