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Hi everyone,
I'm using Hyperlink to transfer data between two C6678 (DSP A and B). One of the Hyperlink segments is mapped on DSP A's MSMC. To perform this transfer, DSP A writes a data on its local MSMC (hyperlink mapped), sends an interruption to DSP B, and DSP B reads the data.
At every execution, the first transfer works successfully, but the second transfer doesn't work : DSP B reads an old value. This issue is probably due to the Cache : I enable L1D and L1P cache and disable L2 cache (I have to keep this configuration).
First I tried to modify MAR register corresponding to MSMC in order to disable cache for this region, but this register (MAR12) is read-only.
So I chose to use XMC to extend this region to 0xA000_0000 and disable cache (with MAR160) with the code at the bottom. I also modified MAR64 register, wich is corresponding to Hyperlink region (0x4000_0000), but it seems to have no effect : DSP B still reads an old value.
I don't know if it's important : when I open ROV > Cache > EnableMARs, I see all MAR registers, except 64 and 160, registers I've modified. However, with MemoryBrowser tool, I can see the right value (0 because I set cacheability and prefetcheability to 0) at 0x0184_8100 (MAR64) and 0x0184_8280 (MAR160).
I use this following code to initialize Cache (wich is coherent with RTSC platform definition and GEL file), XMC and MAR registers.
/*
* Using MPAX register 3
* Segment size : 4 MB (0x15 = 0b10101)
* Logical address : 0xA000_0000 (after DDR3) (0x00A00)
* Physical address : 0x0C00_0000 (MSMC) (0x000C0)
* Protection for supervisor and user : read, write, no execution (110110)
* MAR Register index for 0xA000_0000 : 160 (0xA0)
* */
CACHE_setL1PSize(CACHE_L1_0KCACHE);
CACHE_setL1DSize(CACHE_L1_0KCACHE);
CACHE_setL2Size(CACHE_0KCACHE);
CACHE_setL1PSize(CACHE_L1_0KCACHE);
CACHE_setL1DSize(CACHE_L1_0KCACHE);
CACHE_setL2Size(CACHE_0KCACHE);
CSL_XMC_XMPAXH highStruct = {0x000C0, 0x15};
CSL_XMC_XMPAXL lowStruct = {0x00A00, 1, 1, 0, 1, 1, 0};
CSL_XMC_setXMPAXH(3, &highStruct);
CSL_XMC_setXMPAXL(3, &lowStruct);
CACHE_setMemRegionInfo(160, 0, 0);
CACHE_setMemRegionInfo(64, 0, 0);
To read the data, I use the following line :
Hyplnk_Status[Hyplnk_NumCore] = *((volatile char *)0x40177009);
Does anyone had this issue ?
Thanks for your time.
You'll need to perform writeback invalidates to flush the cached data out to MSMC prior to accesses it via Hyperlink. Manual coherence operations are required on the MSMC SRAM when dealing with multiple Masters (i.e. Hyperlink and a CorePac.)
Best Regards,
Chad
Hi Chad,
Thank you for your reply.
Actually I map Hyperlink window on all the MSMC so I prefer to uncache all the MSMC, it avoids to proceed invalidate and writeback continuously.
I solved the problem : my error was to invert base address and replacement address meaning. A correct code could be :
CSL_XMC_XMPAXH highStruct = {0xA0000, 0x15};
CSL_XMC_XMPAXL lowStruct = {0x00C000, 1, 1, 0, 1, 1, 0};
I also prefer to use CACHE_disableCaching() rather than using CACHE_setMemRegionInfo() : this first function seems to work properly (I don't have the ROV error anymore).
Thanks.
L.G
Hi Chad,
The CACHE_setMemRegionInfo() in CSL can set PCX bit and PFX bit in the MAR registers, but the CorePac user's guide does not describe PCX bit.
How does PCX bit be controlled? Must PCX bit and PC bit be consistent?
This topic is discussed here: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/166571.aspx
Best regards,
Daisuke
Hi,
Here is a new post for PCX bit: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/333040.aspx
Best regards,
Daisuke
Daisuke,
I replied to the other thread, but I'll go ahead and comment here as well.
The PCX bit is for enabling/disabling an external memory (from CorePac perspective) as a cache. For example MSMC is an external shared memory. If has cache capability (potential future devices - non currently available support this) then this would be used to enable the cache. On C6678 which the topic refers to, the device is a Keystone I device and the MSMC does not support a cache mode.
Best Regards,
Chad