Anyone out there using Micron MT47H64M16 DDR2 memory?

Hi Dean,

I am not able to find AISgen screenshot as requested by you. Hope you are looking for DDR2 timing configurations.

Please refer below threads which has more information about Micron MT47H64M16 DDR2(Timing etc)

http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/48626/195543.aspx

http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/108825/386217.aspx

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/266152.aspx

http://e2e.ti.com/support/embedded/linux/f/354/t/153062.aspx

I hope this will solve your issue.

Thanks.

Hi Dean, 

A good way for you to verify your DDR2 timing configurations would be to use the DDR2 timing spreadsheet provided in the wiki link.

Regards,

Rahul

The first link referenced a Hawkboard.  I do have some questions regarding this layout and DDR configuration.  Your other links didn't help at all.  Two of them referenced totally different DSP's with totally different DDR2 configuration registers.

1.  The Harkboard has the ODT pin on the DDR2 memory pulled HIGH.  Our board has the ODT pin pulled LOW.  If I'm reading the C6748 tech manual correctly, it states that ODT is NOT supported.  Furthermore the tech manual says (13.1.5, page 291) "THE ODT PIN MUST BE TIED TO GROUND".  Does it make a difference if the ODT pin is pulled HIGH or LOW?

2.  The Harkboard has a 4.75k pull up resistor on the DDR_CKE line.  I can find no reference to adding a pull up to this line in any of the DDR2 documentation.  Is this pull up necessary?  If not, why is it there?

3.  The Harkboard separates the 1.8V power rail into two parts.  The "normal" 1.8V rail feeds all the VDD1 through VDD5 pins.  The "filtered" 1.8V rail feeds VDDQ1 through VDDQ10 and the VREF node.  Is this required, good design practice, overkill, etc?  Please explain.

4.  The DDR2 configuration values were different compared to ours.  Please comment on each below.

   a)  Hawkboard DDR drive was set to normal drive strength.  Our DDR drive was set to weak.  We don't have any series resistors, and I see the Hawkboard has some on the DDR2 control lines (CS, CKE, CAS, etc).  I believe there is a note somewhere that says if you aren't using series resistors, use weak drive.  Is weak drive correct for our board?

   b)  Hawkboard has Average Periodic Refresh Interval set to 3.9uS, which leads to 585 getting loaded into the RR bit field in the SDRCR register.  The Micron datasheet has this set to 7.8uS, which is the value we used.  Since 7.8uS is the maximum allowed according to the Micron, it seems that the 3.9uS setting would be more forgiving.  Which do you recommend?

   c)  Hawkboard has T_RP set to 1, which leads to 13.33nS.  According to the Micron datasheet, the -3 part (which is what the Harkboard schematic shows is populated) has a minimum of 15nS.  It appears the Hawkboard is overclocking this value.  Comments?

   d)  Hawkboard has T_RCD set to 1, which leads to 13.33nS.  According to the Micron datasheet, T_RCD has a minimum of 15nS.  It appears the Hawkboard is overclocking this value.  Comments?

   e)  Hawkboard has T_WR set to 1, which leads to 13.33nS.  According to the Micron datasheet, T_WR has a minimum of 15nS.  It appears the Hawkboard is overclocking this value.  Comments.

   f)  Hawkboard has T_RAS set to 5, which leads to 40nS.  According to the Micron datasheet, T_RAS has a minimum of 45nS listed in the IDD table, but 40nS listed in the AC Operating table.  Do you know if 40nS or 45nS is correct?

   g)  Hawkboard has T_XSNR set to 19, which leads to 133.33nS.  According to the Micron datasheet, T_XSNR has a minimum of 137.5nS.  It appears the Hawkboard is overclocking this value.  Comments?

   h)  Hawkboad has RL (in the DRPYC1R register) set to 3.  The C6748 tech manual description of this field say it should be:  CAS + round trip board delay - 1.  If we assume CAS = 3, and the round trip board delay to be 1, then this make sense.  How do you calculate the round trip board delay?  Our DDR2 chips is right next to the DSP, so I assume we can use 1, but I'm not 100% certain.  If we make the RL value bigger does that "relax" the timing?

   I)  Hawkboard has EXT_STRBEN set to 0.  The C6748 tech manual says set this to 1 (step #5 Initializing Following Device Power up).  It also mentions setting this to 1 during the Configuring DDR PHY Control Register.  Which is correct 0 or 1?

- Dean

Rahul,

Thanks for pointing out the spreadsheet.  However, I'm VERY aware of this spreadsheet and use it all the time.  A suggestion for improvement.  Create two new tabs.  In one of the tabs, show the most aggressive field settings for a common DDR2 memory (say Micron MT47H64M16).  Maybe even offer some tips and suggestions on why one value was selected vs. a different value.  In the other tab, using the same DDR2 memory, relax the settings and explain what you changed and why.

- Dean

I realize I've asked a ton of questions in my previous post.  If anyone has answers to any of the above questions, please post them.  I'd rather have information trickle in vs. waiting until all the questions have answers.

Thanks, Dean

Dean

I have not had the chance to look at your exhaustive question list and our key DDR expert is out this week. However I saw a lot of refreneces to Hawkboard.

Hawkboard as you might or might not know, is not a good reference from a layout or any other software setting. So comparing anything to the Hawkboard might not be relevant to the discussion, even though our team might've forwarded this link as relevant links to look at.

If you are looking for a good design with DDR2, you can look at the OMAPL138/C6748 LCDK, schematics, layout etc are all on the wiki.

Regards

Mukul

Dean,

What device are you implementing on your board with the DDR2 memory?

Tom

C6748

- Dean

Mukul,

I agree the Hawkboard is a "bad" design.  You can dis-regard the previous post with all the Hawkboard questions.  I've looked at the LCDK board as you recommended.  I have questions related to the RL field in the DRPYC1R register.

1.  How do you calculate round trip board delay, and express that delay in terms of MCLK/DDR_CLK cycles?  If this calculation is explained in the tech manual or datasheet, I've never found it.

2.  The LCDK board uses CL = 4, because that is the lowest value allowed for the memory that was used.  Furthermore the RL field is loaded with 4 for the LCDK board.  Since RL = CL + round trip board delay - 1, that means the round trip board delay for the LCDK is 1.  I've seen this a lot in looking at different boards, CL = RL.  If we have the DDR2 right next to the DSP, can we assume that the round trip board delay is 1?

3.  RL is defined as "helping the memory controller determine when to sample read data".  I've seen references (not on the LCDK) that claim to "relax" the timing, set RL to the max, which is 7.  In order not to violate the RL min / max requirements, you would also have to change CL as well.  If you changed RL to 7, but left CL at 4, wouldn't that screw up the "window" for read data?

4.  Our memory allows a CL of 3.  Even though the DSP and DDR2 support CL = 3, is that too risky to use?  Should we use CL = 4 instead?

Thanks, Dean

I was really hoping to get these questions answered before Friday.  We are expecting our new PCB rev then, and would like to load up the "best" DDR2 timings possible.

Thanks, Dean

Hi Dean,

Dean Hofstetter said:

1.  How do you calculate round trip board delay, and express that delay in terms of MCLK/DDR_CLK cycles?  If this calculation is explained in the tech manual or datasheet, I've never found it.

The TRM reads RL is CAS + 1 or CAS + 2… but the TRM tries to address both DDR and mDDR, so we obtained input directly from design.

TI Designer: For DDR2, the required DDR PHY read latency = CL+1 to CL+3. The programmed value in the register must be minus one the required value. Therefore, programmed value = CL to CL+2.

See TRM SPRUH79A - 13.3.2.4 Configuring DDR PHY Control Register (DRPYC1R)

The DDR PHY control register (DRPYC1R) contains a read latency (RL) field that helps the DDR2/mDDR memory controller determine when to sample read data. The RL field should be programmed to a value equal to the CAS latency plus the round trip board delay minus 1. The minimum RL value is CAS latency plus 1 and the maximum RL value is CAS latency plus 2 (again, the RL field would be programmed to these values minus 1). Table 13-21 shows the resulting DRPYC1R configuration. When calculating round trip board delay the signals of primary concern are the differential clock signals (DDR_CLK and DDR_CLK) and data strobe signals (DDR_DQS). For these signals, calculate the round trip board delay from the DDR memory controller to the memory and then choose the maximum delay to determine the RL value. In this example, we will assume the round trip board delay is one DDR_CLK cycle; therefore, RL can be calculated as: RL = CAS latency + round trip board delay – 1 = 4 + 1 – 1 = 4

Dean Hofstetter said:

2.  The LCDK board uses CL = 4, because that is the lowest value allowed for the memory that was used.  Furthermore the RL field is loaded with 4 for the LCDK board.  Since RL = CL + round trip board delay - 1, that means the round trip board delay for the LCDK is 1.  I've seen this a lot in looking at different boards, CL = RL.  If we have the DDR2 right next to the DSP, can we assume that the round trip board delay is 1?

From a real example, DDR clock is 144MHz, period is 6.9ns, DQGATE trace is 1.65inch, so board delay is 0.3ns (assuming 170 psec/in), which is 0.043 DDR clock cycle – round up to 1

If CL = 4, then RL in range 5 to 7 (programmed value range 4 to 6)

Dean Hofstetter said:

3.  RL is defined as "helping the memory controller determine when to sample read data".  I've seen references (not on the LCDK) that claim to "relax" the timing, set RL to the max, which is 7.  In order not to violate the RL min / max requirements, you would also have to change CL as well.  If you changed RL to 7, but left CL at 4, wouldn't that screw up the "window" for read data?

A value from the high end of the range will always work, but higher value will add extra latency to the read data.

Dean Hofstetter said:

4.  Our memory allows a CL of 3.  Even though the DSP and DDR2 support CL = 3, is that too risky to use?  Should we use CL = 4 instead?

If the memory supports CL = 3 then the RL range is 4 to 6 (programmed value 3 to 5)..

Hope this helps,
Mark

Hey Dean,

Before I answer questions 1 and 2, I was wondering if your PCB is mimicking the layout of an EVM, like the LCDK? If so I would feel comfortable using the same round trip board delay used on that EVM.

If you aren't mimicking: 1. & 2. Please refer to this E2E post. You don't need to read the whole thing, just skip down to the last response, and a very nice description is given on how to calculate round trip board delay. Pay attention to his assumption that FR4 is the PCB material, if it is something different in your case for some reason, you will have to find the correct dielectric constant. Who would've thought you'd have to use electromagnetics equations to do your firmware?! The equation seems very straightforward.

For the I/O buffer time I believe you should reference the C6748 datasheet, section 5.10.6.

3. Yes, 7 is too 'relaxed' for CL=4. For DDR2, the range for acceptable values of RL is CL to CL+2. So for CL = 4, the acceptable range for RL is 4 to 6. This doesn't mean you should just pick 6 'to be safe' and move on; you should still calc the round trip board delay and pick the proper value. But this is an acceptable window.

4. If your memory allows a CL of 3 then it should be ok to use CL = 3. Just need to make sure that RL is set properly in accordance with this value.

I hope this helps.

Thanks, Ian

Mark / Ian,

Thanks for the feedback.  Based on your answers, and looking at other designs (LCDK, 6748EVM, etc), I've come up with the following new values to load into AISGEN.  When looking at the numbers below, remember we are using the DDR2 chip in the title of this post, and our DDR2 clock is 148.8MHz.

SDCR = 0x00174632  (No changes from previous.  DDR drive = weak (no series resistors), CL = 3, and DDR2TERM = 00 per the tech manual)

SDRCR = 0x00000400  (I relaxed this timing slightly.  DDR2 datasheet says 7.8uS max, and our previous setting was 7.795uS.  This new value puts us at 6.88uS)

SDTIMR1 = 0x26923249  (I relaxed two timings.  T_RFC went from 127.69nS to 134.41nS, and T_RC went from 60.48nS to 67.2nS)

SDTIMR2 = 0x3C14C722  (No changes from our previous values)

DRPYC1R = 0x000000C3  (This changed.  RL used to be 4, it is now 3.  See below for more explanation)

I changed RL from 4 to 3 based on a few observations.  The first is our DDR2 layout is similar to the LCDK (DDR2 close to the DSP, short traces, etc).  I then looked at your E2E reference post regarding round trip board delay.  We are using FR4, and our trace length was 1.2".  The only thing I couldn't find in the C6748 datasheet was I/O buffer delay.  Assuming that isn't very big, our round trip board delay is WAY shorter than 6.72nS (based on our 148.8MHz clock).  So we round up and use round trip delay = 1.  Per the RL equation, CL + round trip delay - 1 = 3 + 1 - 1 = 3.

I would appreciate if either of you can use the DDR2 Register Calc spreadsheet and double check everything.  In addition, it appears there is still confusion about RL within TI.  Mark said RL = 7 would ALWAYS work, and Ian said if RL is too large it may not work (depends on board design).  Based on what I have read, I side with Ian.

- Dean

Hey Dean,

Per your last paragraph, there is no confusion between Mark and I, I think we should just be more clear about some terms. When he gives the 'actual' range of RL 5 to 7 he means the actual physical value is 5 to 7. However, this value includes the round trip board delay in it. When we say the "programmable" RL, we mean literally the RL bits in the DRPYC1R control register. So one represents a physical value (which includes board delay, so read latency of 5 to 7 for a cl=4) and one represents what you need to actually program into the device (RL from 4 to 6 if CL=4). Does that make more sense now? I find the programmable value better suited to talk about as this is what you'll actually be plugging into the register, but mine and Mark's answers are in essence the same, he just references both the real and the programmable values.

As for the DDR2 Register Calc:

-Assuming you intended to set the DDRDRIVE0 bit,  I got your SDCR register values as well

-I can got your SDRCR values as well

-Using the RegCalc tab, T_RFC=134.41nS I get 0x28923249. Using T_RFC=134nS, I get the same as you, 0x26923249. However, plugging 0x26923249 into the RegDecode gives me 134.41nS. That's odd to me. I don't have experience with the spreadsheet but it seems that the RegDecode is a bit more reliable. 

-Since you didn't change anything on SDTIMR2 I will assume you did this correctly

-The RegDecode tab makes it seem like you did this one right. I noticed on RegCalc it always assumes that RL = CL + 1. So maybe that tab needs a bit of work.

Hope this helps.

-Ian

Hey Dean,

Where you able to work everything out with the new board?

-Ian

Nope, we struck out with the Rev. 6 PCB.  Roughly 50% of the boards lock up, which is similar to previous shop orders.  So the hunt continues.

Thanks for looking at my DDR2 timings.  Not only did I intend to set the DDRDRIVE0 bit, I believe I MUST set this bit.  Our layout doesn't use series resistors.  According to section 5.11.3.9, subnote (4) from Table 5-33, if no serial terminators are used, the DDR2 must be programmed to operate in 60% strength mode.  In addition, this article http://processors.wiki.ti.com/index.php/DDR_Interface_Drive_Strength says that weak drive must also be used if no serial terminators are used.  Do you agree?

May I suggest that someone at TI (yourself, or someone else) take the C6748 datasheet / spreadsheet plus the Micron datasheet, and calculate the DDR2 timings without looking at my answers.  Then after you have arrived at your timings compare them to mine.  If they are different, we can discuss why.

I would like to continue to relax the DDR2 timings.  Can you suggest new relaxed timings?

Thanks, Dean

Dean,

I agree about the drive strength settings.

As for using the datasheet, I did reference both the C6748's and the memory's datasheets for parameters when I used the spreadsheet. Besides what I said above, I everything agreed with you.

As for relaxing your timings, I would again have  you look at the links provided by Rajasekaran, particularly this one: http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/48626/195543.aspx#195543 . You can see down the page that the issue was resolved by matching the Hawkboard timings. I know that it was stated that the hawkboard is not a good hardware reference but I think that it would be worthwhile to at least compare your timings to the Hawkboards. If there are any discrepencies you could try to adopt the hawkboard timings. It seemed to work for some other people with your problems where they specifically said their settings were too 'tight'.

-Ian

If I'm going back to the Hawkboard, then I'd like all my questions answered about that board and its timings.  My questions are a few posts back, and they were never answered.  From what I understand, the Hawkboard layout has multiple problems and a lot of the DDR2 timings are overclocking the DDR2 memory.  While they may have worked for a few people, the Hawkboard seems to be a step in the wrong directions.

I have referenced the LCDK board, and its timings are very close to mine.  In the places we differ, my timings are more relaxed.

I'm attempt a new twist right now.  Leave the CL = 3 in the SDCR register, and change RL = 4 in the DRPYC1R register.  Even though our board delay worked out to well below 1 clock, RL = 4 should be still a valid value.

The one thing I can't seem to get over, is how many designs use series resistors, and thus need the DDR2 drive set to FULL.  Maybe the C6748 DDR2 drive set to weak isn't fully qualified?

- Dean

Well the RL = 4 didn't help.  I may try RL = 5 latter, but there doesn't seem to be much point.  I think I've beat up the DDR2 timings as much as possible.  Thanks for your help.

- Dean