Issue with tuning the DDR PHY on TI814x devices with SW leveling.

Vaibhav,

You have DDR memory chips attached to both EMIF controllers (EMIF0 and EMIF1), right?

Vaibhav Dhingani said:

The values for EMIF1 should be this?

I think this depends on the trace length used. Per my understanding, if the trace length is the same for both EMIFs, you can apply the EMIF0 values to EMIF1 also.

This is what we have regarding EMIF1:

http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot

Select Script -> TI814x DDR Configuration -> DDR3_EMIF0_EMIF1_400MHz_Config

CortxA8: GEL Output: DM814x DDR3 EVM EMIF0 and EMIF1 configuration in progress.........

CortxA8: GEL Output: DM814x DDR3 EVM EMIF0 and EMIF1 configuration is DONE. . 

Note:

1. SW leveling has to be performed on each EMIF separately and each PHY configured accordingly if the trace lengths are significantly different for each EMIF.
2. The slave ratio program expects EMIF0 to be configured for a base address of 0x8000:0000 and EMIF1 to be at oxC000:0000. The DMM LISA registers has to be configured accordingly as shown in the File:TI814x ddr3.zip gel file. Please note that user can choose a different base address for the DDR memory space (if needed) post the SW leveling.

The values obtained in the previous step need to be plugged under the TI814X appropriate #define in the order emif0 : emif 1. There are seperate macro for each byte lane suffixed with BYTE<n>

/* TI814X DDR3 PHY CFG parameters <emif0 : emif 1> */ 
#define DDR3_PHY_RD_DQS_CS0_BYTE0 ((emif == 0) ? 0x38 : 0x3A) 
#define DDR3_PHY_RD_DQS_CS0_BYTE1 ((emif == 0) ? 0x37 : 0x36) 
#define DDR3_PHY_RD_DQS_CS0_BYTE2 ((emif == 0) ? 0x32 : 0x37) 
#define DDR3_PHY_RD_DQS_CS0_BYTE3 ((emif == 0) ? 0x31 : 0x33) 
#define DDR3_PHY_WR_DQS_CS0_BYTE0 ((emif == 0) ? 0x43 : 0x49) 
#define DDR3_PHY_WR_DQS_CS0_BYTE1 ((emif == 0) ? 0x44 : 0x4E) 
#define DDR3_PHY_WR_DQS_CS0_BYTE2 ((emif == 0) ? 0x53 : 0x54) 
#define DDR3_PHY_WR_DQS_CS0_BYTE3 ((emif == 0) ? 0x50 : 0x50) 
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE0 ((emif == 0) ? 0xE4 : 0xD3) 
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE1 ((emif == 0) ? 0x111 : 0xF7) 
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE2 ((emif == 0) ? 0x112 : 0x109) 
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE3 ((emif == 0) ? 0x13D : 0x135) 
#define DDR3_PHY_WR_DATA_CS0_BYTE0 ((emif == 0) ? 0x85 : 0x8A) 
#define DDR3_PHY_WR_DATA_CS0_BYTE1 ((emif == 0) ? 0x83 : 0x80) 
#define DDR3_PHY_WR_DATA_CS0_BYTE2 ((emif == 0) ? 0x85 : 0x7F) 
#define DDR3_PHY_WR_DATA_CS0_BYTE3 ((emif == 0) ? 0x7F : 0x85)

http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot_Wordwise_SWleveling

The calculated compensation values are assumed to apply to both EMIF0 and EMIF1. However if trace lengths differ significantly between EMIF0 and EMIF1 on customers board, they may have to supply separate values for EMIF0 and EMIF1.

For Asymmetric DDR2/3 memory interface(Where trace lengths of DDR0 & DDR1 for CK & DQS are different), then DDR3_slave_ratio_search.out should be run twice to calculate the Slave Ratio values for DDR0(Memory Map Address =0x8000_0000) & DDR1(Memory Map Address).

For Symmetric DDR2/3 memory interface(Where trace lenghts of DDR0 & DDR1 for CK & DQS are almost equal or exactly equal) , then DDR2_slave_ratio.search.out can be run for DDR0 interface only to calculate the Slave ratio values and use same slave ratio values for DDR1 interface also.

BR
Pavel

Hi Pavel,

We are working on this DDR sw leveling tuning and like to ask you a question.

When we look into u-Boot code "ddr_defs_ti814x.h", the defines are as follows:

#define DDR3_PHY_RD_DQS_CS0_DEFINE ((emif == 0) ? 0x30 : 0x30)
#define DDR3_PHY_WR_DQS_CS0_DEFINE ((emif == 0) ? 0x21 : 0x21)
#define DDR3_PHY_RD_DQS_GATE_CS0_DEFINE ((emif == 0) ? 0xC0: 0xC0
#define DDR3_PHY_WR_DATA_CS0_DEFINE ((emif == 0) ? 0x44 : 0x44)

The defines are not separated according to _BYTE0, _BYTE1, _BYTE2, _BYTE3.

How should the generated output to input to the u-boot code?

Thank you

Regards

May

Hi May,

Lee, May Fong said:

When we look into u-Boot code "ddr_defs_ti814x.h"

This file is from u-boot-2010.06-psp04.04.00.01, correct?

Please note that we have the below u-boot patch available in the arago-project:

http://arago-project.org/git/projects/?p=u-boot-omap3.git;a=commit;h=507bb282bb1b92fa1d7d10556addc474b612823b

Best regards,
Pavel

Hi Pavel,

Thank you for the patch.

We managed to get the DDR software leveling to work.

Regards

May