DDR PHY Tuning Issues

I am following the process provided at http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_In to tune the DDR PHY on a DM816x device on a custom board for environmental testing. These boards are fully operational and execute our mission software. I have followed the procedure to the letter and I am having issues. When I execute the DDR3_796MHZ_doall hotmenu from the TI816x_DDR3.gel file, I immediately get the following output:

CortexA8: Output: Device type is GP

CortexA8: Output: DM816x Main PLL Init is in Progress, Please wait .....

CortexA8: Output: DM816x Main PLL Init is Done .....

CortexA8: Output: DM816x DDR PLL Init is in Progress for 796.5 MHz DDR Clock, Please wait .....

CortexA8: Output: DM816x DDR PLL Init is Done .....

CortexA8: Output: DM816x DDR2/3 PRCM Init is in progress .....

CortexA8: Output: DM816x DDR2/3 PRCM Init is Done .....

After about 15 seconds or so, I get the following error:

CortexA8: Trouble Writing Memory Block at 0x4c000010 on Page 0 of Length 0x4: (Error -2130 @ 0x4C000010) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.520.0)

DDR3_796MHZ_doall() cannot be evaluated.

target access failed

The failure occurs at the following lines 2139 - 2141 of the function EMIF4P_Init in the T1816x_DDR3.gel (downloaded from the site mentioned above) when attempting to write the the SDRAM Refresh Control Register at address 0x4C000010:

WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, 0x0000613B); /* initially a large refresh period */

WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, 0x1000613B); /* trigger initialization */

WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, (0x10000000|SDREF)); /* move to a smaller more correct one */

When I comment out the lines mentioned above, I make it completely through the script:

CortexA8: Output: Device type is GP

CortexA8: Output: DM816x Main PLL Init is in Progress, Please wait .....

CortexA8: Output: DM816x Main PLL Init is Done .....

CortexA8: Output: DM816x DDR PLL Init is in Progress for 796.5 MHz DDR Clock, Please wait .....

CortexA8: Output: DM816x DDR PLL Init is Done .....

CortexA8: Output: DM816x DDR2/3 PRCM Init is in progress .....

CortexA8: Output: DM816x DDR2/3 PRCM Init is Done .....

CortexA8: Output: Initializing EMIF1 .....

CortexA8: Output: DDR3 SWLEVELING DONE FOR EMIF0

CortexA8: Output: DDR3 SWLEVELING DONE FOR EMIF1

CortexA8: Output: DM816x EMIF Init is Done @ 796.5 MHz Clock Rate.....

CortexA8: Output: PRCM for OCMCRAM0/1 Initialization in Progress

CortexA8: Output: OCMCRAM0 & OCMCRAM1 Accesses are PASSED

CortexA8: Output: PRCM for OCMCRAM0/1 Initialization in Done

From here, if I continue with the procedure and execute the DDR3_SlaveRatio_ByteWiseSearch_TI816x.out file via Run->Load->Load Program... menu, the program loads and runs; however, nothing is printed to the console and I am never prompted for the DDR Controller number or seed values. If I suspend execution and step through the Disassembly, the CortexA8 appears to be stuck in a loop executing the following instruction:

EAFFFFFE B 0x2008C

At this point I am unclear how to proceed. We are carefully following the instructions, including setting the Boot Mode / Configuration Select Switches all to off.

We are running CCS verison is 5.1.0.09000 and using a XDS560v2 STM probe. Our DDR3 is running at 800MHz and is fully functional. I have repeated the above procedure with the Wordwise leveling instructions with the same results. I have even tried running the other DDR3_xMHZ_doall hotmenu scripts with the same result.