PROCESSOR-SDK-AM64X: DDR control register, DDR phy register, DDR phy Independent register where is the data from

Hello Jun,

Thank you for reaching out to Texas Instruments E2E support forum.

I have taken you inputs and working on it. Please allow some time to revert back.

Regards,

Tushar

Jun, as you have found out, the controller/PHY is quite complex with many register configurations.  We have a DDRSS Register Configuration tool here:  dev.ti.com/sysconfig which will help facilitate configuration of these registers.  You need to choose the correct device, and then the GUI will present a bunch of parameters based on the DDR type and design that you have.  Default values for the EVMs can be chosen if you are working with those boards.  The README link has instructions on how to use the tool

Regards,

James

1.
I appreciate any assistance you can provide in understanding how the default configurations for these registers are determined, including the underlying considerations or criteria influencing these values.

2.

I have an additional question regarding the TMDS64GPEVM demo board. Despite completely deleting the register configurations, specifically for the DDR (Double Data Rate) registers, the board continues to function properly. Does this imply that there are default values already present in these DDR registers, eliminating the need for explicit configurations?

Here is my DDR configuration code, and it's evident that I removed all the functions below. During debugging, I observed that these functions are not even utilized.

 I removed:

<code>

int32_t DDR_init()
{

DDR_socEnableVttRegulator();

/* power and clock to DDR and EMIF is done form outside using SysConfig */

/* Configure MSMC2DDR Bridge Control register. Configure REGION_IDX, SDRAM_IDX and SDRAM_3QT.*/
HW_WR_REG32_RAW((CSL_DDR16SS0_SS_CFG_BASE + 0x20), 0x1EF);

/* Configure DDRSS_ECC_CTRL_REG register. Disable ECC. */
HW_WR_REG32_RAW((CSL_DDR16SS0_SS_CFG_BASE + 0x120), 0x00);

}
</code>

Thanks. 

for question 2:
I am loading  load_dmsc_hsfs.js  to reset M4 core. maybe in that one, had ddr phy default value also.

2. for js file. 
To seek additional verification, do the lines of code within the "load_dmsc_hsfs.js" file initialize DDR as depicted below?

<code>
  print("Running the board configuration initialization from R5!");
// Load the board configuration init file.
dsMCU1_0.memory.loadProgram("tools/ccs_load/am64x/sciclient_ccs_init.release.out");
</code>

1.  
Furthermore, I am awaiting your responses to question 1. Could you provide an explanation about the the DDR  registers values and what they are based?

we can take demo board TMDS64GPEVM  as example.  

Thanks.

2. Yes, that is for the main board configuration, including DDR.  You can read more about sciclient here:  board_ddrReginit.h

1. The register values will be based on the memory that is on the EVM board.  The Register Configuration Tool was used to generate the appropriate configuration file to properly initialize the memory on the EVM 

Regards,

James

Thanks,  Question2 is resolved.

let me put my question1 in this way. In your sdk tool I saw you provide a ddr4 configuration as follows:

However, the parameter on the left side only encompasses approximately 100 registers, whereas there are a total of 1000 registers.

For instance, consider the scenario where I intend to utilize MT40A1G16 as my DDR module.

(You can find the datasheet for MT40A1G16 at this link:  https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr4/16gb_ddr4_sdram.pdf)

Question:

Will your default configuration be compatible with DDR4 MT40A1G16?

I am referring to an additional 1000 registers that cannot be configured using your tool. Is it acceptable for them to remain as default?

Thanks