AM4378: Difference in DDR PHY control register settings

shigehiro tsuda

Part Number: AM4378

Hi,

On our customer's board, there is a difference in the operation with the setting of DDR3 register below.
Regarding this bit, there is no detailed description in TRM, so please tell me what kind of behavior it will be by setting.

EMIF4D_DDR_PHY_CTRL_1 Register
RDLVL_MASK,RDLVLGATE_MASK,WRLVL_MASK bit

OK setting:

EMIF4D_DDR_PHY_CTRL_1 = 0x0004800A
EMIF4D_EXT_PHY_CTRL_1 = 0x10040100

Fail setting:

EMIF4D_DDR_PHY_CTRL_1 = 0x0E04800A
EMIF4D_EXT_PHY_CTRL_1 = 0x10040100

In u-boot, this bit is set,
This bit is not set for the gel file included with CCS.
Is the leveling method different?

u-boot
u-boot\board\ti\am43xx\board.c

CCS gel
ccsv7\ccs_base\emulation\boards\evmam437x\gel\AM43xx_EMIFconfig_HWlvl.gel

Best Regards,
Shigehiro Tsuda

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

The DRR experts have been notified. They will respond here. Please make sure you follow correctly the procedure outlined in www.ti.com/.../sprac70.pdf for tuning the EMIF.

0 sivak over 8 years ago in reply to Biser Gatchev-XID

TI__Genius 9655 points

Tsuda-san,

Which version of u-boot are you using? I presume you are using DDR3. Can you confirm?

EMIF4D_DDR_PHY_CTRL_1 Register bits you referred are related to HW leveling and appears to be disabled in u-boot.

Regards, Siva

0 Steve Kipisz over 8 years ago in reply to sivak

TI__Genius 15510 points

Also, what version of the SDK are you using?

Steve K.

0 shigehiro tsuda over 8 years ago in reply to Steve Kipisz

Mastermind 9490 points

Hi Siva and Steve,

Thank you for quick reply.

They use DDR3L.
They use ti-processor-sdk-linux 01.00.00.03.
Since the SDK they are using was old, I checked the u-boot of SDK 4.00.00.04, but the same value seems to be set.

Since the following sources are called and ext_phy_settings_hwlvl () is being executed, I think that hardware leveling is being executed.
u-boot\arch\arm\cpu\armv7\am33xx\ddr.c

Best Regards,
Shigehiro Tsuda

0 shigehiro tsuda over 7 years ago in reply to sivak

Mastermind 9490 points

Hi,

Is there any update information?

Best Regards,
Shigehiro Tsuda

0 Steve Kipisz over 7 years ago in reply to shigehiro tsuda

TI__Genius 15510 points

Hello,

We are looking into this.

Steve K.

0 shigehiro tsuda over 7 years ago in reply to Steve Kipisz

Mastermind 9490 points

Hi Steve,

Thank you for quick reply.
Is there any update information?

Our customers are having trouble starting problems, so we want answers as soon as possible.

Best Regards,
Shigehiro Tsuda

0 shigehiro tsuda over 7 years ago in reply to Steve Kipisz

Mastermind 9490 points

Hi Steve,

Is there any update information?
Our customers are having market trouble with their products, so it seems that they want an answer as soon as possible.
Please answer as soon as possible.

Best Regards,
Shigehiro Tsuda

0 Steve Kipisz over 7 years ago in reply to shigehiro tsuda

TI__Genius 15510 points

The values that work should be used. I am going to file a ticket for the software team to fix this.

Steve K.

0 Steve Kipisz over 7 years ago in reply to Steve Kipisz

TI__Genius 15510 points

The values will be in a future release of the SDK.

Steve K.

0 shigehiro tsuda over 7 years ago in reply to Steve Kipisz

Mastermind 9490 points

Hi Steve,

Thank you for the reply.
Which value will be updated in the future SDK?

Best Regards,
Shigehiro Tsuda

0 sivak over 7 years ago in reply to shigehiro tsuda

TI__Genius 9655 points

For DDR3, the values will be updated to support HW leveling i.e. the pass setting you have here. Let me know if you have any more questions

Regards, Siva

0 shigehiro tsuda over 7 years ago in reply to sivak

Mastermind 9490 points

Hi Siva,

Thank you for the reply.
I understood that HW leveling will be updated to a value to be supported.

Best Regards,
Shigehiro Tsuda

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AM4378: Difference in DDR PHY control register settings