Tool/software: Linux
Hello,
Below is the sample ddr3 structure for am43xx. I wanted to understand the purpose of the phy registers and their relationship with levelling.
I have gone through the
Below is the register used for configuration:
const struct emif_regs ddr3_emif_regs_400Mhz_idk = { .sdram_config = 0x61A11B32, .ref_ctrl = 0x00000C30, .sdram_tim1 = 0xEAAAD4DB, .sdram_tim2 = 0x266B7FDA, .sdram_tim3 = 0x107F8678, .read_idle_ctrl = 0x00050000, .zq_config = 0x50074BE4, .temp_alert_config = 0x0, emif_ddr_phy_ctlr_1 = 0x00008009, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x00700070, .emif_ddr_ext_phy_ctrl_3 = 0x00700070, .emif_ddr_ext_phy_ctrl_4 = 0x00700070, .emif_ddr_ext_phy_ctrl_5 = 0x00700070, .emif_rd_wr_exec_thresh = 0x00000405, .emif_prio_class_serv_map = 0x00000000, .emif_connect_id_serv_1_map = 0x00000000, .emif_connect_id_serv_2_map = 0x00000000, .emif_cos_config = 0x00FFFFFF }; emif_ddr_phy_ctlr_1 = 0x00008009, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x00700070, .emif_ddr_ext_phy_ctrl_3 = 0x00700070, .emif_ddr_ext_phy_ctrl_4 = 0x00700070, .emif_ddr_ext_phy_ctrl_5 = 0x00700070,const u32 ext_phy_ctrl_const_base_ddr3_idk[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00700070, 0x00350035, 0x00350035, 0x00350035, 0x00350035, 0x00350035, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00340034, 0x00340034, 0x00340034, 0x00340034, 0x00340034, 0x00000000, 0x00600020, 0x40010080, 0x08102040 };