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Linux/AM4378: DDR PHY registers and leveling

Part Number: AM4378

Tool/software: Linux

Hello,

Below is the sample ddr3 structure for am43xx. I wanted to understand the purpose of the phy registers and their relationship with levelling.

I have gone through the 

http://processors.wiki.ti.com/index.php/AM437x_DDR_Configuration_and_Programming_Guide

 

Below is the register used for configuration:
   
const struct emif_regs ddr3_emif_regs_400Mhz_idk = {
    .sdram_config           = 0x61A11B32,
    .ref_ctrl           = 0x00000C30,
    .sdram_tim1         = 0xEAAAD4DB,
    .sdram_tim2         = 0x266B7FDA,
    .sdram_tim3         = 0x107F8678,
    .read_idle_ctrl         = 0x00050000,
    .zq_config          = 0x50074BE4,
    .temp_alert_config      = 0x0,
     emif_ddr_phy_ctlr_1        = 0x00008009,
    .emif_ddr_ext_phy_ctrl_1    = 0x08020080,
    .emif_ddr_ext_phy_ctrl_2    = 0x00700070,
    .emif_ddr_ext_phy_ctrl_3    = 0x00700070,
    .emif_ddr_ext_phy_ctrl_4    = 0x00700070,
    .emif_ddr_ext_phy_ctrl_5    = 0x00700070,
    .emif_rd_wr_exec_thresh     = 0x00000405,
    .emif_prio_class_serv_map   = 0x00000000,
    .emif_connect_id_serv_1_map = 0x00000000,
    .emif_connect_id_serv_2_map = 0x00000000,
    .emif_cos_config        = 0x00FFFFFF
};
Can you clarify the purpose of these registers .emif_ddr_ext_phy_ctrl_1 to .emif_ddr_ext_phy_ctrl_5  and if they matter if hardware levelling is selected.
     emif_ddr_phy_ctlr_1        = 0x00008009,
    .emif_ddr_ext_phy_ctrl_1    = 0x08020080,
    .emif_ddr_ext_phy_ctrl_2    = 0x00700070,
    .emif_ddr_ext_phy_ctrl_3    = 0x00700070,
    .emif_ddr_ext_phy_ctrl_4    = 0x00700070,
    .emif_ddr_ext_phy_ctrl_5    = 0x00700070,
Also, What is the purpose of below these registers? Are they also required if hardware levelling is selected?
const u32 ext_phy_ctrl_const_base_ddr3_idk[EMIF_EXT_PHY_CTRL_CONST_REG] = {
    0x00700070,
    0x00350035,
    0x00350035,
    0x00350035,
    0x00350035,
    0x00350035,
    0x00000000,
    0x00000000,
    0x00000000,
    0x00000000,
    0x00000000,
    0x00340034,
    0x00340034,
    0x00340034,
    0x00340034,
    0x00340034,
    0x00000000,
    0x00600020,
    0x40010080,
    0x08102040
};
Thanks
  • Hi,

    The wiki guide you refer is now superseded by: www.ti.com/.../sprac70.pdf Please follow the guidelines in the new document. This is all the information necessary to configure the AM437x EMIF.
  • Hi Biser,

    Thanks for your response. I have followed the xls sheet found in the wiki and set the following values

    We are using 2 x MT41K256M16TW-107 (512MB DDR). Total - 1024MB.
    We have calculated the following values from the excel sheet. Also, we have added the trace length from the layout.
    We find that the bootloader hangs during the x-loader after setting the ddr3 values shown below (calculated from the excel sheet for AM437x). We dont have JTAG connectivity therefore,
    we cant run the CCS Software.
    I wanted to check if MT41K256M16TW-107 has been used in AM437x. 

    Please let me know if i am missing something here.

    EMIF Registers

    Register

    Address

    Value

    EMIF4D_SDRAM_TIMING_1

    0x4C000018

    0xE88AE4E3

    EMIF4D_SDRAM_TIMING_1_SHADOW

    0x4C00001C

    0xE88AE4E3

    EMIF4D_SDRAM_TIMING_2

    0x4C000020

    0x26377FDA

    EMIF4D_SDRAM_TIMING_2_SHADOW

    0x4C000024

    0x26377FDA

    EMIF4D_SDRAM_TIMING_3

    0x4C000028

    0x5F7F867F

    EMIF4D_SDRAM_TIMING_3_SHADOW

    0x4C00002C

    0x5F7F867F

    EMIF4D_SDRAM_CONFIG

    0x4C000008

    0x61A01332

    EMIF4D_SDRAM_CONFIG_2

    0x4C00000C

    0x00000000

    EMIF4D_SDRAM_REFRESH_CTRL

    0x4C000010

    0x00000C30

    EMIF4D_SDRAM_REFRESH_CTRL_SHADOW

    0x4C000014

    0x00000C30

    EMIF4D_SDRAM_OUTPUT_IMPEDANCE_CALIB_CNG

    0x4C0000C8

    0x50077D33

    EMIF4D_LPDDR2_MODE_REG_CONFIG

    0x4C000050

    0x80000000

    EMIF4D_LPDDR2_MODE_REG_DATA

    0x4C000040

    0x00000000

    EMIF4D_TEMPERATURE_ALERT_CONFIG

    0x4C0000CC

    0x00000000

    EMIF4D_READ_WRITE_LEVELING_RAMP_WINDOW

    0x4C0000D4

    0x00000000

    EMIF4D_READ_WRITE_LEVELING_RAMP_CTRL

    0x4C0000D8

    0x80000000

    EMIF4D_READ_WRITE_LEVELING_CTRL

    0x4C0000DC

    0x00000000

    Register

    Address

    Value

    EMIF4D_DDR_PHY_CTRL_1

    0x4C0000E4

    0x00048008

    EMIF4D_DDR_PHY_CTRL_1_SHADOW

    0x4C0000E8

    0x00048008

    EMIF4D_EXT_PHY_CTRL_1

    0x4C000200

    0x00040100

    EMIF4D_EXT_PHY_CTRL_1_SHADOW

    0x4C000204

    0x00040100

    EMIF4D_EXT_PHY_CTRL_2

    0x4C000208

    0x00000000

    EMIF4D_EXT_PHY_CTRL_2_SHADOW

    0x4C00020C

    0x00000000

    EMIF4D_EXT_PHY_CTRL_3

    0x4C000210

    0x00000000

    EMIF4D_EXT_PHY_CTRL_3_SHADOW

    0x4C000214

    0x00000000

    EMIF4D_EXT_PHY_CTRL_4

    0x4C000218

    0x00000000

    EMIF4D_EXT_PHY_CTRL_4_SHADOW

    0x4C00021C

    0x00000000

    EMIF4D_EXT_PHY_CTRL_5

    0x4C000220

    0x00000000

    EMIF4D_EXT_PHY_CTRL_5_SHADOW

    0x4C000224

    0x00000000

    EMIF4D_EXT_PHY_CTRL_6

    0x4C000228

    0x00000000

    EMIF4D_EXT_PHY_CTRL_6_SHADOW

    0x4C00022C

    0x00000000

    EMIF4D_EXT_PHY_CTRL_7

    0x4C000230

    0x00400040

    EMIF4D_EXT_PHY_CTRL_7_SHADOW

    0x4C000234

    0x00400040

    EMIF4D_EXT_PHY_CTRL_8

    0x4C000238

    0x00400040

    EMIF4D_EXT_PHY_CTRL_8_SHADOW

    0x4C00023C

    0x00400040

    EMIF4D_EXT_PHY_CTRL_9

    0x4C000240

    0x00400040

    EMIF4D_EXT_PHY_CTRL_9_SHADOW

    0x4C000244

    0x00400040

    EMIF4D_EXT_PHY_CTRL_10

    0x4C000248

    0x00400040

    EMIF4D_EXT_PHY_CTRL_10_SHADOW

    0x4C00024C

    0x00400040

    EMIF4D_EXT_PHY_CTRL_11

    0x4C000250

    0x00400040

    EMIF4D_EXT_PHY_CTRL_11_SHADOW

    0x4C000254

    0x00400040

    EMIF4D_EXT_PHY_CTRL_12

    0x4C000258

    0x00400040

    EMIF4D_EXT_PHY_CTRL_12_SHADOW

    0x4C00025C

    0x00400040

    EMIF4D_EXT_PHY_CTRL_13

    0x4C000260

    0x00400040

    EMIF4D_EXT_PHY_CTRL_13_SHADOW

    0x4C000264

    0x00400040

    EMIF4D_EXT_PHY_CTRL_14

    0x4C000268

    0x00400040

    EMIF4D_EXT_PHY_CTRL_14_SHADOW

    0x4C00026C

    0x00400040

    EMIF4D_EXT_PHY_CTRL_15

    0x4C000270

    0x00400040

    EMIF4D_EXT_PHY_CTRL_15_SHADOW

    0x4C000274

    0x00400040

    EMIF4D_EXT_PHY_CTRL_16

    0x4C000278

    0x00400040

    EMIF4D_EXT_PHY_CTRL_16_SHADOW

    0x4C00027C

    0x00400040

    EMIF4D_EXT_PHY_CTRL_17

    0x4C000280

    0x00000000

    EMIF4D_EXT_PHY_CTRL_17_SHADOW

    0x4C000284

    0x00000000

    EMIF4D_EXT_PHY_CTRL_18

    0x4C000288

    0x00000000

    EMIF4D_EXT_PHY_CTRL_18_SHADOW

    0x4C00028C

    0x00000000

    EMIF4D_EXT_PHY_CTRL_19

    0x4C000290

    0x00000000

    EMIF4D_EXT_PHY_CTRL_19_SHADOW

    0x4C000294

    0x00000000

    EMIF4D_EXT_PHY_CTRL_20

    0x4C000298

    0x00000000

    EMIF4D_EXT_PHY_CTRL_20_SHADOW

    0x4C00029C

    0x00000000

    EMIF4D_EXT_PHY_CTRL_21

    0x4C0002A0

    0x00000000

    EMIF4D_EXT_PHY_CTRL_21_SHADOW

    0x4C0002A4

    0x00000000

    EMIF4D_EXT_PHY_CTRL_22

    0x4C0002A8

    0x00000000

    EMIF4D_EXT_PHY_CTRL_22_SHADOW

    0x4C0002AC

    0x00000000

    EMIF4D_EXT_PHY_CTRL_23

    0x4C0002B0

    0x00600020

    EMIF4D_EXT_PHY_CTRL_23_SHADOW

    0x4C0002B4

    0x00600020

    EMIF4D_EXT_PHY_CTRL_24

    0x4C0002B8

    0x40010080

    EMIF4D_EXT_PHY_CTRL_24_SHADOW

    0x4C0002BC

    0x40010080

    EMIF4D_EXT_PHY_CTRL_25

    0x4C0002C0

    0x08102040

    EMIF4D_EXT_PHY_CTRL_25_SHADOW

    0x4C0002C4

    0x08102040

    EMIF4D_EXT_PHY_CTRL_26

    0x4C0002C8

    0x00200020

    EMIF4D_EXT_PHY_CTRL_26_SHADOW

    0x4C0002CC

    0x00200020

    EMIF4D_EXT_PHY_CTRL_27

    0x4C0002D0

    0x00200020

    EMIF4D_EXT_PHY_CTRL_27_SHADOW

    0x4C0002D4

    0x00200020

    EMIF4D_EXT_PHY_CTRL_28

    0x4C0002D8

    0x00200020

    EMIF4D_EXT_PHY_CTRL_28_SHADOW

    0x4C0002DC

    0x00200020

    EMIF4D_EXT_PHY_CTRL_29

    0x4C0002E0

    0x00200020

    EMIF4D_EXT_PHY_CTRL_29_SHADOW

    0x4C0002E4

    0x00200020

    EMIF4D_EXT_PHY_CTRL_30

    0x4C0002E8

    0x00200020

    EMIF4D_EXT_PHY_CTRL_30_SHADOW

    0x4C0002EC

    0x00200020

    EMIF4D_EXT_PHY_CTRL_31

    0x4C0002F0

    0x00000000

    EMIF4D_EXT_PHY_CTRL_31_SHADOW

    0x4C0002F4

    0x00000000

    EMIF4D_EXT_PHY_CTRL_32

    0x4C0002F8

    0x00000000

    EMIF4D_EXT_PHY_CTRL_32_SHADOW

    0x4C0002FC

    0x00000000

    EMIF4D_EXT_PHY_CTRL_33

    0x4C000300

    0x00000000

    EMIF4D_EXT_PHY_CTRL_33_SHADOW

    0x4C000304

    0x00000000

    EMIF4D_EXT_PHY_CTRL_34

    0x4C000308

    0x00000000

    EMIF4D_EXT_PHY_CTRL_34_SHADOW

    0x4C00030C

    0x00000000

    EMIF4D_EXT_PHY_CTRL_35

    0x4C000310

    0x00000000

    EMIF4D_EXT_PHY_CTRL_35_SHADOW

    0x4C000314

    0x00000000

    EMIF4D_EXT_PHY_CTRL_36

    0x4C000318

    0x000000FF

    EMIF4D_EXT_PHY_CTRL_36_SHADOW

    0x4C00031C

    0x000000FF

    IO Registers

    CTRL_DDR_CKE

    0x44E1131C

    0x00000003

    CTRL_DDR_ADDRCTRL_IOCTRL

    0x44E11404

    0x00000084

    CTRL_DDR_ADDRCTRL_WD0_IOCTRL

    0x44E11408

    0x00000000

    CTRL_DDR_ADDRCTRL_WD1_IOCTRL

    0x44E1140C

    0x00000000

    CTRL_DDR_DATA0_IOCTRL

    0x44E11440

    0x00000084

    CTRL_DDR_DATA1_IOCTRL

    0x44E11444

    0x00000084

    CTRL_DDR_DATA2_IOCTRL

    0x44E11448

    0x00000084

    CTRL_DDR_DATA3_IOCTRL

    0x44E1144C

    0x00000084

    CTRL_EMIF_SDRAM_CONFIG_EXT

    0x44E11460

    0x0000C163

  • Can you share the spreadsheet that was used to create these values?

    Regards, Siva

  • SPRAC70_AM437x_EMIF_Configuration_Tool_V20_05092017_TEST.xlsx

    sivak said:

    Can you share the spreadsheet that was used to create these values?

    Regards, Siva

    Please find attached the excel sheet that we used.

  • There are several errors in the spreadsheet. Please review the documentation in the link for more details:
    www.ti.com/.../sprac70.pdf

    Step1 System Details:
    - Detail 6 is related to the speed grade that the memory device is going to be operated at. For AM437x, it should be 800 since you cannot run the DDR interface at >400MHz clock.
    - Detail 7 should be 4Gb not 0.5Gb. This is the density of individual DRAM part

    Step2 DDR Timings
    - Select the correct CL/CWL based on the memory datasheet
    - Input all the DRAM AC timing parameters by referencing the memory data sheet. This is required to generate the right timing register settings. Make sure you review all the RED boxes since they indicate violation w.r.t. min JEDEC specifications.

    After you fix the spreadsheet and obtain new register values, please try again and let us know if you still face any issues.

    Regards, Siva
  • I have Detail 6 noted incorrectly above. Please see below with correction.

    There are several errors in the spreadsheet. Please review the documentation in the link for more details:
    www.ti.com/.../sprac70.pdf

    Step1 System Details:
    - Detail 6 is related to the speed grade that the memory device capability. For DRAM part you indicated, it should be 1866 and select CL=13 to pick the right speed bin table column. The actual value of CL/CWL is programmed in Step 2 as indicated below
    - Detail 7 should be 4Gb not 0.5Gb. This is the density of individual DRAM part

    Step2 DDR Timings
    - Select the correct CL/CWL based on the memory datasheet and speed of operation i.e. tCK setting
    - Input all the DRAM AC timing parameters by referencing the memory data sheet. This is required to generate the right timing register settings. Make sure you review all the RED boxes since they indicate violation w.r.t. min JEDEC specifications.

    After you fix the spreadsheet and obtain new register values, please try again and let us know if you still face any issues.

    Regards, Siva
  • Hi Siva,

    1. I tried as suggested. However, When i use the values generated by the excel sheet in the u-boot. It still hangs in MLO.

    2. Therefore, I think i might be missing something here. I would request your help and advice on this.

    3. I have attached the xls file for your reference.

    4. CAS is 13. But Sheet2 (DDR Timings) allows only 5 or 6.

    6. Similarly, CWL is 9 according to the datasheet. But excel sheet allows only 5. However 5 is also supported (Page 80)

    7. tCKESR. It is 4CK, However, AC Operating conditions dont have a "ns" value for this item. (Page 96)

    Looks like i am missing something here. Attached is my excel sheet for your reference.SPRAC70_AM437x_EMIF_Configuration_Tool_V20_TRIAL2_VSR.xlsx

    Thanks,

    Sriram

  • Hi Siva,

    I wanted to check if you got a chance to look at my spreadsheet. There are 2 DDR3 chips (512 MB each). DDR3-1 is connected to DDR-data0 to DDR-data15 of AM437x and DDR3-2 chip is connected to DDR-data16 to DDR-data31 of AM437x. Does this mean that DDR Data bus Width Per EMIF is 16 or 32. I have tried both of them but with the same result.

    Speed bin for the chip is 1866. The datasheet also says that it is backward compatible to 1600 speed bin. Does this mean that i can consider this chip to be 1600 speed bin and select the DDR timing values corresponding to the speed bin of 1600?

    For 1600, If i take (CL = 7 and CWL = 6) or (CL=8 and CWL=6) the tck is less than 2.5ns which probably is less than 400MHZ, however, the excel sheet does not allow this.

    Please let us know if i am missing something here.

    Thanks,

    Regards,
    Sriram
  • Sriram V said:

     
    I wanted to check if you got a chance to look at my spreadsheet. There are 2 DDR3 chips (512 MB each). DDR3-1 is connected to DDR-data0 to DDR-data15 of AM437x and DDR3-2 chip is connected to DDR-data16 to DDR-data31 of AM437x. Does this mean that DDR Data bus Width Per EMIF is 16 or 32. I have tried both of them but with the same result.

    Under 1A) System application details, Detail 3 i.e. DDR Data Bus Width per EMIF should be set as 32. This is representing the DDR data bus width of the controller that you intend to use. Under 1B) DDR memory specification, Detail 12 is the width of the data bus of the individual DRAM part. In your case, it should be set as x16
     

    Sriram V said:

    Speed bin for the chip is 1866. The datasheet also says that it is backward compatible to 1600 speed bin. Does this mean that i can consider this chip to be 1600 speed bin and select the DDR timing values corresponding to the speed bin of 1600?

    In the Step1-System Details section, under 1B) DDR memory specifications, Detail 6 you should specify the capability of the DRAM memory part. Therefore, in your case 1866 is the right setting. This is basically used to refer to the speed bin tables that is used for Step2-DDR Timings.

    Sriram V said:


    For 1600, If i take (CL = 7 and CWL = 6) or (CL=8 and CWL=6) the tck is less than 2.5ns which probably is less than 400MHZ, however, the excel sheet does not allow this. 
     
      

    As I mentioned above, for your case, you should be setting the speed grade i.e. Detail 6 as 1866 and select your CAS latency as 13 to reflect the right speed bin table for the memory part that you have used. This Table is on Page 80 of the DRAM memory data sheet that you pointed to earlier.

    You still have some errors in the Step2-DDR Timings sheet. Any timings that don't meet JEDEC requirements are automatically highlighted in RED. You need to refer to the memory data sheet and fix them. In your case, for instance I see tRP, tRCD are not set correctly. They need to be set as 13.91 instead of 12.5 in the spreadsheet. Please verify the same for all the other timing parameters to make sure there are no errors and match the data sheet
    On Step-3 make sure you also add all the board routing details for the CLK and DQS for each Byte to arrive at the right invert clock setting.
    Once you do all the above, please see if the board still fails. If so, then I suggest you work off a simple GEL file to help you debug what could be causing this failure.
    Regards, Siva

  • Hi Siva,

    1. As suggested, I used a Gel File AM43xx_EMIFConfig_Hwlvl.gel and am able to run the ddr tests and it works fine. I ported the u-boot test code to CCS and it also works fine along with DDR tests found in the Gel Files.

    2. I then used the same values which are generated by the excel sheet into u-boot 2016. I am using mtest to test my ddr3

    3. Memory test mtest 0x80000000 0xA0000000 Passes. However mtest 0xA0000000 0xC0000000 fails at

         FAILURE (read/write) @ 0xbef1db60: expected 0x07bc76d9, actual 0x07bc76d8)

    4. When i try to do a mw 0xbef1db60 0x99 and try to read it back. I dont see my value reflected at 0xbef1db60. please find the attached uboot mtest log for some of the errors.

    5. I am not sure what could be the issue here. However, with the same values Both the Gel file and u-boot give different results.

    6. The Page size is 2K according to the datasheet. Therefore i chose tFAW and tRRD values which are applicable for 2048. Let me know if this is fine?

    I am not sure if the hardware levelling is done in the same way in u-boot and gel file. Please let me know if i am missing anything here.

    Below is the hardware levelling status register values. Thanks for your help.

    Dump of Phy Status Registers in uboot

    --------------------------------------

    => md 0x4c00144

    4c000144: 000841f3 1a0d0683 0db60004 00020db6

    4c000154: 00009999 00000924 00000049 00000045

    4c000164: 00000046 00000046 00000000 070000aa

    4c000174: 070000ac 070000b8 070000b3 00000000

    4c000184: 027f00c1 01bc00c8 029700d3 02ff00d4

    4c000194: 00000000 023f0081 017c0088 02570093

    4c0001a4: 02bf0094 00000000 10f02322 00000000

    U-boot Phy Status Values:

    PHY_STATUS_12=0x00000924

    PHY_STATUS_13=0x00000045

    PHY_STATUS_14=0x00000046

    PHY_STATUS_15=0x070000aa

    PHY_STATUS_16=0x070000b8

    PHY_STATUS_7 =0x00000049

    PHY_STATUS_8 =0x00000045

    PHY_STATUS_9 =0x00000046

    PHY_STATUS_10=0x00000046

    PHY_STATUS_11=0x00000000

    PHY_STATUS_17=0x027F00C1

    PHY_STATUS_18=0x01bc00c8

    PHY_STATUS_19=0x029700D3

    PHY_STATUS_20=0x02ff00d4

    PHY_STATUS_21=0x00000000

    PHY_STATUS_22=0x023F0081

    PHY_STATUS_23=0x017c0088

    PHY_STATUS_24=0x02570093

    PHY_STATUS_25=0x02bf0094

    PHY_STATUS_26=0x00000000

    Dump of Phy Status Registers in CCS

    ------------------------------------

    CortexA9: GEL Output: PHY_STATUS_12=0x070000A9

    CortexA9: GEL Output: PHY_STATUS_13=0x070000AC

    CortexA9: GEL Output: PHY_STATUS_14=0x070000BA

    CortexA9: GEL Output: PHY_STATUS_15=0x070000B7

    CortexA9: GEL Output: PHY_STATUS_16=0x00000000

    CortexA9: GEL Output: PHY_STATUS_7 =0x00000048

    CortexA9: GEL Output: PHY_STATUS_8 =0x00000045

    CortexA9: GEL Output: PHY_STATUS_9 =0x00000048

    CortexA9: GEL Output: PHY_STATUS_10=0x00000046

    CortexA9: GEL Output: PHY_STATUS_11=0x00000000

    CortexA9: GEL Output: PHY_STATUS_17=0x027F00C1

    CortexA9: GEL Output: PHY_STATUS_18=0x01BC00BD

    CortexA9: GEL Output: PHY_STATUS_19=0x029700D3

    CortexA9: GEL Output: PHY_STATUS_20=0x02FF00D3

    CortexA9: GEL Output: PHY_STATUS_21=0x00000000

    CortexA9: GEL Output: PHY_STATUS_22=0x023F0081

    CortexA9: GEL Output: PHY_STATUS_23=0x017C007D

    CortexA9: GEL Output: PHY_STATUS_24=0x02570093

    CortexA9: GEL Output: PHY_STATUS_25=0x02BF0093

    CortexA9: GEL Output: PHY_STATUS_26=0x00000000

    My EMIF Values which i used to feed to Gel and U-boot are: 3073.SPRAC70_AM437x_EMIF_Configuration_Tool_V20_1866_190917.xlsx

    Some of the u-boot mtest failures are as follows: uboot.txt

  • 1. I tried mtest on the AM437x IDK board. I am using a complete test (CONFIG_SYS_ALT_MEMTEST) which is more exhaustive. I find that that it returns errors similar to mine. IDK board uses harware levelling for DDR.

    2. I am using ti-processor-sdk-linux-am437x-evm-03.03.00.04. My u-boot  top commit points to 4db46a6bbde46e4587b77e14763787f66c292701. I am using the default u-boot sources and i have enabled mtest support in defconfig file.

    3. Please find the below error. I am not sure if we are missing something with h/w levelling support in u-boot.

    => mtest 0xA0000000 0xC0000000

    Testing a0000000 ... c0000000:

    Iteration:      1

    FAILURE (read/write) @ 0xbef0fda0: expected 0x07bc3f69, actual 0x07bc3f68)

    3. Therefore, I wanted to check if i am missing something here. Below is my defconfig patch to enable the mtest.

    #define CONFIG_CMD_MEMTEST             1

    #define CONFIG_SYS_ALT_MEMTEST         1

    #define CONFIG_SYS_MEMTEST_START       (0x84000000)            /* memtest */                                    

    #define CONFIG_SYS_MEMTEST_END         (0xC0000000)          

    #define CONFIG_SYS_MEMTEST_SCRATCH     (CONFIG_SYS_MEMTEST_START - 4)  /* dummy address */

    idk_uboot.txt
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    U-Boot SPL 2016.05-00321-gf0b98c6 (Sep 20 2017 - 19:33:48)
    Trying to boot from MMC1
    SPL: Please implement spl_start_uboot() for your board
    SPL: Direct Linux boot not active!
    reading u-boot.img
    reading u-boot.img
    reading u-boot.img
    reading u-boot.img
    U-Boot 2016.05-00321-gf0b98c6 (Sep 20 2017 - 19:33:48 +0530)
    CPU : AM437X-GP rev 2.0
    Model: TI AM437x Industrial Development Kit
    DRAM: 1 GiB
    PMIC: TPS62362
    NAND: 0 MiB
    MMC: OMAP SD/MMC: 0
    reading uboot.env
    ** Unable to read "uboot.env" from mmc0:1 **
    Using default environment
    Net:
    Warning: ethernet@4a100000 using MAC address from ROM
    eth0: ethernet@4a100000
    Hit any key to stop autoboot: 0
    =>
    =>
    =>
    => mtest 0x80000000 0xA0000000
    Testing 80000000 ... a0000000:
    Iteration: 2
    => <INTERRUPT>
    => <INTERRUPT>
    => <INTERRUPT>
    => <INTERRUPT>
    => <INTERRUPT>
    => <INTERRUPT>
    => <INTERRUPT>
    => <INTERRUPT>
    => <INTERRUPT>
    => <INTERRUPT>
    => <INTERRUPT>
    => <INTERRUPT>
    => mtest 0xA0000000 0xC0000000
    Testing a0000000 ... c0000000:
    Iteration: 1
    FAILURE (read/write) @ 0xbef0fda0: expected 0x07bc3f69, actual 0x07bc3f68)
    FAILURE (read/write): @ 0xbef0f860: expected 0xf843c1e6, actual 0x00000020)
    FAILURE (read/write): @ 0xbef0f864: expected 0xf843c1e5, actual 0x0000000f)
    FAILURE (read/write): @ 0xbef0f868: expected 0xf843c1e4, actual 0x00000004)
    FAILURE (read/write): @ 0xbef0f86c: expected 0xf843c1e3, actual 0x00000001)
    FAILURE (read/write): @ 0xbef0f874: expected 0xf843c1e1, actual 0x63316531)
    FAILURE (read/write): @ 0xbef0f878: expected 0xf843c1e0, actual 0x36333331)
    FAILURE (read/write): @ 0xbef0f8b8: expected 0xf843c1d0, actual 0x00000020)
    FAILURE (read/write): @ 0xbef0f8bc: expected 0xf843c1cf, actual 0xbef0f99f)
    FAILURE (read/write): @ 0xbef0f8c0: expected 0xf843c1ce, actual 0xbff72d5f)
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • Hello,

    Any updates on this? I would request you to help me on this. Thanks,

    Regards,
    Sriram
  • I'll ask our SW team to check this.

    Regards, Siva
  • Hi Siva,

    Did you get any updates from your S/W Team on why exhaustive memtest in u-boot are failing in the region of 0xBf0000000...0xC0000000 when CONFIG_SYS_ALT_MEMTEST is enabled on the AM437x IDK platform with the TI Processor SDK.

    Thanks for your help and support once again.
  • mem.sh.gzThe EMIF settings in u-boot show that hardware leveling is enabled. U-boot relocates itself to upper memory so I think you are trying to overwrite u-boot. The Processor SDK has a memory test utility in the file system that is very extensive. I have attached a script so that you only need to pass in the % of memory you want to test. The output looks like this

    Loop 1:

     Stuck Address       : ok

     Random Value        : ok

     Compare XOR         : ok

     Compare SUB         : ok

     Compare MUL         : ok

     Compare DIV         : ok

     Compare OR          : ok

     Compare AND         : ok

     Sequential Increment: ok

     Solid Bits          : ok

     Block Sequential    : ok

     Checkerboard        : ok

     Bit Spread          : ok

     Bit Flip            : ok

     Walking Ones        : ok

     Walking Zeroes      : ok

    gunzip the file and simply type in ./mem.sh <% memory to test>

    Steve K.

  • Hi Steve,

    Thank you for responding to this question.

    Well, I have used memtester in Linux and it passed. However, coming back to the problem in u-boot. u-boot has 2 different tests, A simple/quick test and an exhaustive test. The exhaustive test is very comprehensive.

    I ran the test from 0x84000000 0xC0000000. Everytime, it fails between 0xBf0000000...0xC0000000

    I have seen the same issue in my custom board as well as the AM437x IDK board without making any change. I have enabled the exhaustive tests on the idk board only.

    On my custom AM437x board, If i disable levelling the same test passes. Which makes me wonder what could be wrong as a result,
    Due to this I have disabled the last 16MB because i am not sure what is wrong.

    Thanks for your help.
  • Can you make sure you are not overwriting u-boot itself? u-boot relocates itself to upper memory and runs from there.

    Steve K.