Need TI experts' opinion on debug interfaces on OMAP 3503

JTAG is used for loading and control of the CPU(s) and BSDL. At a minimum, you need JTAG, as it will help you debug through power states (see here: http://tiexpressdsp.com/index.php/ICEPICK#Q:_I_am_using_OMAP3.2C_are_there_any_special_features_for_debugging_through_power_transitions.3F)

ETM simply outputs the tracing for the ARM core, which is useful for profiling and debugging. You need JTAG to control the ETM.

In general I only use and see used JTAG, as you suggest it is more common for debugging. I suspect the other interfaces can be useful and provide deeper debugging detail (i.e. hardware trace), however I think the limiting factor on them is the cost of the tools, in particular I believe you need to use ARM's own tools to leverage ETM (i.e. RealView and a Lauterbach emulator).

EDIT: Steve is right, for some reason I thought using the ETM was unsupported in CCS, I suspect my knowledge is out of date there, the wiki article Steve suggests looks like a great place to start.

Actually, on OMAP3, with just JTAG, they could access the ETB: http://tiexpressdsp.com/index.php/ETB

Hi.

Did you ever try to program the ETM from within the core to output profiling applications on an OMAP3 processor?

I have done this successfully for a PB1176jzf-s dev. board's ARM1176 development chip and was trying to port my sources.

However I currently can't access the registers for a OMAP3530 (Beagleboard rev c3) and am looking for a solution. I think the IO slice of the registers is disabled and I need to enable it or enable/program the necessary IO clock for the slice to non zero.

From within the Cortex-A8 core the ETM software accessible memory base address should be:

- either 0x54010000(what I think should be the software base if I am to look at the ETB bases for JTAG TAP memory access and L3-L4 interconnect memory access)

- or 0xd4010000 (JTAG TAP mapping).