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C6455 SRIO initialization ERROR problem.

Yongfeng Ma
Prodigy 115 points

Hi,

   We have a C6455 EVM to check the SRIO program. We use the example program 'master_slave' and modify it to 1x mode. It works well on the EVM. But when I run the same program on our C6455 board, it fails. I find out that:

1, It fails during the SRIO nitialization, that is the SRIO link can't handshake. It loops the following code. Also, if I run the SLAVE DSP before the MASTER DSP , the SLAVE will fail to pass the loop code and the MASTER DSP can pass. If I run the MASTER DSP before the SALVE DSP, the MASTER will fail to pass the loop code and the SLAVE DSP can pass. Who runs first, who  die!

do {
        status = CSL_srioHwSetup (hSrio, &setup);
        if (status != CSL_SOK) {
         printf("SRIO: ... Hardware setup, failed\n");
            return;
        }
  delay(100000);
        CSL_srioGetHwStatus (hSrio, CSL_SRIO_QUERY_SP_ERR_STAT, &response);
    } while(response.data & 0x1);

2,The SRIO CLK on the EVM is 25MHz vs. our board 156.25MHz;

3,The EVM is point to point connected via 4x SRIO vs.our board via 1x SRIO, there 4 DSPs  on our board interconnected via SRIO.

4,I can't find other difference.

But WHY the SAME code can't run on our board?

I hope to get your message!

Thanks.

            Ma Yongfeng .

 

 

 

  • 0
    TI__Guru* 84110 points

    Two suggestions to try:

    1. Try configuring the EVM with 1x SRIO to eliminate that difference. With just software changes like you have done for your board, you can configure the EVM SRIO to be used as 4 1x links instead of 1 4x link. If you can get a single 1x link working there, then you will be much closer to solving your problem with your board.
    2. Make certain that the big clock difference is not causing a problem. This is a substantial and non-integer change in clock rate, so care must be taken to make sure you have everything configured right for the change.
  • 0 in reply to RandyP
    Prodigy 115 points

    Thank you RandyP!

    I have tried configuring the EVM with 1x SRIO and even cut off one of the four lanes to make it sure.So it is really working in 1x mode on the EVM.

    I will check the clock difference and hope to work! Thank you again!

  • 0 in reply to Yongfeng Ma
    Prodigy 115 points

    HI, I have settled the problem yesterday. 

    I change the SRIO ref clock from 156.25MHz to 125MHz and insert some delay in the program. It is OK. WHY?

  • 0 in reply to Yongfeng Ma
    TI__Guru* 84110 points

    Very good that you have your SRIO working now.

    What calculations did you make when you decided to use 156.25MHz? Did you make any adjustments in the settings to account for this clock change?

  • 0 in reply to RandyP
    Prodigy 115 points

    In fact, the hardware is designen by  another engineer , the 156.25MHz is selected optionally.

    Yes,I changed some settings...

    pSetup->periCntlSetup.prescalar = CSL_SRIO_CLK_PRESCALE_6;

    pSetup->serDesPllCfg[0].pllMplyFactor = CSL_SRIO_SERDES_PLL_MPLY_BY_10;

    pSetup->portIpPrescalar = 25;

    Some of them is not so clear to me.

    I have to read the datasheet carefully.

    It is a good place to discuss problems here, but my English is poor....