HI.
Below are my two functions for setting up the PLL and the CODEC ...........i want codec to be slave, codec(aic3204) WHICH has a PLL which receive input from the I2S BCLK port also the same for the WCLK.
The problem is i dont get valid samples
* Configuring the Clock*/
/*void Set_PLL(void) {
CONFIG_SW = 0x0; // Bypass the PLL
PLL_CNTL2 = 0x8000;
PLL_CNTL4 = 0x0000;
PLL_CNTL3 = 0x0806;
PLL_CNTL1 = 0x8BB4;
while ( (PLL_CNTL3 & 0x0008) == 0) CONFIG_SW = 0x1; //Switch to the PLL after configuration of PLL
}
*/
Int16 AIC3204_rset( Uint16 regnum, Uint16 regval )
{
Uint8 cmd[2];
cmd[0] = regnum & 0x007F; // 7-bit Register Address
cmd[1] = regval; // 8-bit Register Data
return USBSTK5515_I2C_write( AIC3204_I2C_ADDR, cmd, 2 ); }
void Codec_setting(void) {
Int16 data1, data2, data3, data4;
USBSTK5515_init( );
SYS_EXBUSSEL = 0x6100; // Enable I2C bus
USBSTK5515_I2C_init( );
// Setting up the Codec for Capturing the data
AIC3204_rset( 0, 0 ); // initialize to page 0 of the Memory Map.
AIC3204_rset( 1, 1 ); // Software Reset to initialize all the register.
AIC3204_rset( 0, 1 ); // Selecting the page 1 of the Memory Map.
AIC3204_rset( 1, 0x088 ); // Disable crude AVDD generation from DVDD.
AIC3204_rset( 71, 0x31 ); // Analogue input charge-time (3.1ms)
AIC3204_rset(123, 0x01 ); // REF charging time 40ms
AIC3204_rset( 2, 0x00 ); // Enable Analog Blocks, use LDO power, voltage set =1.67
AIC3204_rset( 0, 0 ); // re-selecting page 0 of the Memory Map.
AIC3204_rset(27,0x00); // 0x0d Setting the WCLK and BCLK as o/p to AIC3204(Master) Using Audio Interfacing Register1
AIC3204_rset(28,0x00); // The data offset set to Zero.
AIC3204_rset( 4, 0x07 ); //....Setting the CODEC_CLKIN to be PLL Output(0x47) going to ADC/DAC
AIC3204_rset( 6, 0x08 ); // Clock setting register,PLL CODEC setting: J=8
AIC3204_rset( 7, 0x00 ); //.... PLL setting: HI_BYTE(D=1680)
AIC3204_rset( 8, 0x00); // ....PLL setting: LO_BYTE(D=1680)
//AIC3204_rset( 30, 0x00 ); // 0x088For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, 0xA1 ); // PLL setting: Power up PLL, P=2 and R=1
AIC3204_rset( 13, 0x00 ); // .........Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x40 ); // .........Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x40 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x84 ); // Power up NDAC and set NDAC value to 4
AIC3204_rset( 12, 0x84 ); // Power up MDAC and set MDAC value to 4
AIC3204_rset( 18, 0x84 ); // Power up NADC and set NADC value to 4
AIC3204_rset( 19, 0x84 ); // Power up MADC and set MADC value to 4
// DAC ROUTING AND POWER UP
AIC3204_rset( 0,0x01 ); // Select page 1
AIC3204_rset(12 ,0x08); //Route left DAC to HPL
AIC3204_rset(13 ,0x08); //Route RIGHT DAC to HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL
// AIC3204_rset( 66, 0x00 ); // ....Right DAC gain to 0dB VOL
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel DAC Channel set up
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 16, 0x10 ); // Unmute HPL , 0dB gain
AIC3204_rset( 17, 0x10 ); // Unmute HPR , 0dB gain
AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
USBSTK5515_wait( 500 ); // Wait
// ADC ROUTING AND POWER UP
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 51, 0x00 ); // Disable BIAS
AIC3204_rset( 52, 0x0C ); // STEREO 1 Jack
// IN2_L to LADC_P through 40 kohm
AIC3204_rset( 55, 0x0C ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 57, 0xc0 ); // common mode to RADC_M through 40 kohm
AIC3204_rset( 59, 0x00 ); // Unmute left MIC PGA Gain selection of 6dB to make channel gain 0dB
AIC3204_rset( 60, 0x00 ); // Unmute right MIC PGA Gain selection of 6dB to make channel gain 0dB
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 81, 0x0C ); // Powerup Left and Right ADC Channels
AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC
AIC3204_rset( 0, 0 );
USBSTK5515_wait( 200 ); // Wait
/* I2S settings */
I2S0_CR = 0x8012; // I2SSCTRR 16-bit word, slave, enable I2C
I2S0_SRGR = 0x2a; //I2SSRATE Register should be configured if I2S0 is the master
I2S0_ICMR = 0x0028; // Enable interrupts
//Polling the Data
while (1){
while((Rcv & I2S0_IR) == 0) { // Wait for interrupt pending flag
data3 = I2S0_W0_MSW_R; // 16 bit left channel received audio data
data1 = I2S0_W0_LSW_R;
data4 = I2S0_W1_MSW_R; // 16 bit right channel received audio data
data2 = I2S0_W1_LSW_R;}
/* Write Digital audio */
while((Xmit & I2S0_IR) == 0){ // Wait for interrupt pending flag
I2S0_W0_MSW_W = data3; // 16 bit left channel transmit audio data
I2S0_W0_LSW_W = 0;
I2S0_W1_MSW_W = data4; // 16 bit right channel transmit audio data
I2S0_W1_LSW_W = 0;}
}
}
