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Hi,
We are testing our custom board based on 66AK2H06. We are facing issues with ddr_reset_workaround in U-Boot.
DDR3A PGSR0 and DDR3B PGSR0 always detects leveling errors. Write Leveling Error, DQS Gate Training Error, Write Leveling Adjustment Error bits are always set for both DDR3A and DDR3B.
We disabled the DDR reset workaround in U-Boot temporarily and postponed the investigation. We did not face any issues with DDR. But when we started doing reboot tests for the board and we see that after approx 60 reboots, the DDR initialization fails. The problem observed was similar to that KeyStoneII.BTS_errata_advisory.21 (DDR3 Leveling issue). Before enabling the ddr_rest_workaround, we have figure out why PGSR0 status reports leveling errors all the time.
We are using Samsung K4B2G1646Q-BCK0 device and tested both Speed grades 1333 and 1600.
Please let us know how to proceed on this issue.
Thanks
Rams
Rams,
Your problem report is confusing in the way that you present the results from your different tests. Please describe each test and then the result for it clearly. I think you have 2 tests:
1. Standard configuration sequence as contained in uboot code from TI:
Does this fail leveling on DDR3A and DDR3B on every test run?
Does leveling fail on DDR3A and DDR3B on every board tested?
2. You modified the configuration sequence to disable the DDR reset workaround:
It appears that it now executes without leveling error. Is this true?
Was removal of the DDR reset the only change?
This test failed after 60 reboots. Did both DDR3A and DDR3B fail or just one of them?
The DDR3 layouts must meet the length matching rules stated in the DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1B). Some PCB layout tools can generate length matching reports automatically. Otherwise this will need to be generated by hand. Please provide this report for review. Below is an example for a discrete layout (this is easier for DIMM layouts):
The attached spreadsheet is useful for calculating the proper register settings. It will be released on the K2H web page in the next few weeks. Please fill out this spreadsheet and attach it.
4137.K2 DDR3 Register Calc v1p51.xlsx
We request that customers validate their board design using a GEL file for configuration. Have you done this? Please provide this GEL file containing the above calculated register values for review. If you need the latest K2HK EVM GEL file, it can be downloaded in the latest EMU pack at: http://software-dl.ti.com/sdoemb/sdoemb_public_sw/ti_emupack_keystone2/1_1_0_0/exports/ti_emupack_keystone2_setup_1.1.0.0.exe
Tom
Hi Tom,
Please find the DDR3 layout report spreadsheet and the DDR3 configuration of our custom board.
Let me know your comments.
Thanks
Rams
Rams,
The length matching for the Clock, Address, Command and Control nets is not complete. These must be routed in a fly-by configuration. Then the routes must be length matched for each segment. For instance, lets assume the fly-by connections are:
DSP -> SDRAM1 -> SDRAM2 -> SDRAM3 -> SDRAM4 -> VTT_terminations
Then the length matching must show the rule are met for:
DSP -> SDRAM1
DSP -> SDRAM2
DSP -> SDRAM3
DSP -> SDRAM4
Please provide this information.
Tom
Sverre,
That is not sufficient. You need to match the lengths as I said:
DSP -> SDRAM1
DSP -> SDRAM2
DSP -> SDRAM3
DSP -> SDRAM4
If you match SDRAM to SDRAM, then you are including stub routing twice in the calculations. Via placement can also cause incorrect fly-by length matching. Fly-by routing must be individually length matched from the DSP to each SDRAM. Please populate the table with this information.
Tom
Hi Tom!
We have made some updates.
On the B-bank there are some small violations (less than 2.5 mils) in command/address lines if we calculate in this way.
DDR3_length_matching :
Those small violations would not cause 100% failure. There is something more fundamental here. However, the layout should be improved in a future revision to obtain the required margins for robustness.
You indicated that you tested at 1300 and 1600. Did you see the same failure at both speeds?
I am still waiting for a completed K2 REG_CALC spreadsheet. The spreadsheet and associated App Note are now on the K2H TI product page. Also, we need to know whether you see the same failure when using a TI-provided GEL file which has been updated with the register values associated with your design. It is too complicated to debug a board layout through uboot debugging.
Tom
Sverre,
The DDR3 length matching template provided actually is from the C6678 EVM also produced by Advantech. The spreadsheet is formatted in an easily understandable format. As a template, it is equally applicable for K2 DDR3 layouts.
Tom