TMS320C672x EMIF bus with FPGA

Prad

Expert 1125 points

Hi,

In our application we have to connect two TMS320C672x to a FPGA through EMIF,

in order to save the FPGA ports, we are connecting with a common bus to FPGA as shown below,

I would like to know that, when one of the DSP is active and using this common bus,

should the other DSP's EMIF kept in high impedance?

Thankyou in advance.

over 15 years ago

0 Gus Martinez over 15 years ago

TI__Mastermind 28891 points

This hookup will be an issue for you. According to the EMIF user guide, the EMIF always drives the data bus when EMIF is idle. This is done to avoid floating pins. The EMIF stops driving the data bus during reads. See "Data Bus Parking" in the C672x EMIF user guide (SPRU711).

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TMS320C672x EMIF bus with FPGA