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TMS320C6726B: TMS320C672x SPI Module DAT Registers

Part Number: TMS320C6726B

Hello,

I was wondering what the difference is between SPIDAT0[15:0] and SPIDAT1[15:0] for this DSP.  According to the SPI datasheet (SPRU718B), SPIDAT0 is the "main shift register", and SPIDAT1 is for "automatic slave chip select mode only".  I don't understand what ""automatic slave chip select mode" is, but ultimately we want to use the SPI in 5-pin master mode.  I notice that the example code in section B.2 of the SPI datasheet writes to SPIDAT0 in 5-pin master mode, but apparently my colleagues believe that only SPIDAT1 can be used in this case.

Thanks,

Alec

  • Hi Alec,

    See these E2E threads. I think the SPI peripheral is the same (or very simlar).

    e2e.ti.com/.../217077

    e2e.ti.com/.../157135

    e2e.ti.com/.../279718

    There is a SPI example that can be found in the C672x CSL:
    processors.wiki.ti.com/.../Chip_support_library

    Refer also to Appendix B.1 Programming SPI.

    SPIDAT1 has some formatting bits that you may need to configure, but writing to those bits will not trigger a new transfer.
    It looks like writing to the LSBs of SPIDAT1 or any bits of SPIDAT0 will trigger a transfer.
    I'll dig around the documents to see if I can find anything that might shed more light on SPIDAT1 usage over SPIDAT0.

    Hope this helps,
    Mark
  • Okay, thanks Mark.

    From one of the links you provided, it sounds like the SPI transfer settings at SPIDAT1[31:16] *may* exclusively be applied to SPI transfers via SPIDAT1[15:0] and not SPIDAT0[15:0], though this is not clear -- I guess I could try to test this with a scope.

    However, since we have already tested and verified that things work when just using SPIDAT1, I will just continue to exclusively use SPIDAT1 and assume there's nothing major we are missing.
  • Sounds good Alec,

    Let us know if you get around to proving it with the scope. It may benefit others as the documentation is a little bit unclear.

    Regards
    Mark