Question about nNMI pin of AM437x

g.f.

Guru 15510 points

Hi,

I have questions about AM437x interrupt.

There are external interrupt pin nNMI(G25pin).

Q1.

From AM437x TRM(spruhl7b) page.1106 Table 8-1 ARM Cortex-A9 Interrupts,

nmi_int is correspond to Int#39, so it seems that it is maskable interrupt.

Is nNMI non-maskable interrupt?

Or is it maskable interrupt like the other interrupts?

Q2.

How long does it take to detect the assertion of nNMI interrupt by AM437x?

Q3.

After nNMI assertion, does it affect to AM437x pins status and the internal state of AM437x?

Q4.

When nNMI interruption occurs, does AM437x do any special processing automatically for nNMI?

Or is the processing just like the other maskable interrupts?

best regards,

g.f.

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi g.f,

Q1: It is a maskable interrupt, like the others.

Q2: The nNMI line is hooked directly to the interrupt controller, which is part of the A9 MPU, so there are no latencies over processor interconnects.

Q3: I don't understand this question.

Q4: No, processing is like any other interrupt.

0 g.f. over 9 years ago in reply to Biser Gatchev-XID

Guru 15510 points

Hi Biser,

Thank you for the reply.

I understood about the Q1,Q2,Q4.
Sorry, but please forget about the Q3.

By the way, is nNMI interrupt low level-sensitive?
If yes, is there a timing requirment about how long to keep it to low level?

best regards,
g.f.

0 Biser Gatchev-XID over 9 years ago in reply to g.f.

TI__Guru**** 393215 points

Yes, it's level sensitive, active level is low. There is no timing requirement published so far.

0 g.f. over 9 years ago in reply to Biser Gatchev-XID

Guru 15510 points

Hi Biser,

Thank you for the quick reply.
I understood.

best regards,
g.f.

Processors

Processors forum

Question about nNMI pin of AM437x