AM335x Using the Ratio Seed spreadsheet for DDR3

Hi,

The spreadsheet is attached here:RatioSeed_AM335x_boards.xlsx

Are all the calculated values correct?

Best regards,

Daisuke

Hi Daisuke-san,

You should use PHY_INVERT_CLKOUT=1.

Daisuke Maeda said:

but the CMDx_PHY_CTRL_SLAVE_RATIO shows "100" which is beyond "80h" as the upper limit of the register value

80h is the reset default value, usable field is 10 bits long. Same usable field size is valid for DATAx_PHY_FIFO_WE_SLAVE_RATIO registers.

Hi Biser-san,

Thank you for your reply.

TRM(SPRUH73L) describes this:

Best regards,

Daisuke

Hi Biser-san,

Here is a post about CMDx_PHY_CTRL_SLAVE_RATIO: e2e.ti.com/.../380453

If the spreadsheet(8053.RatioSeed_AM335x_boards.xlsx) shows "100" for CMDx_PHY_CTRL_SLAVE_RATIO, is it correct to set 100h to the register?

Best regards,

Daisuke

I have asked for clarification on this.

Hi Biser-san,

Thank you for your help.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hi Biser-san,

Our customer tried the software leveling with PHY_INVERT_CLKOUT=1. It showed that all optimal values are 0.

Are these values correct?

Best regards,

Daisuke

I have asked for support on this but no answer so far. Today I asked again. Sorry for the delay.

Values with MIN=0 and MAX=0 are not correct.

You have a non-working RAM.

Hi Wolfgang and Biser,

Thank you for your reply.

When the register values for MT41J512M8RH-125 on EVM in U-Boot are applied to their board, the access to DDR3 RAM works fine. Therefore their RAM should be a working RAM.

 /* Micron MT41J512M8RH-125 on EVM v1.5 */

 #define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006

 #define MT41J512M8RH125_EMIF_TIM1   0x0888A39B

 #define MT41J512M8RH125_EMIF_TIM2   0x26517FDA

 #define MT41J512M8RH125_EMIF_TIM3   0x501F84EF

 #define MT41J512M8RH125_EMIF_SDCFG   0x61C04BB2

 #define MT41J512M8RH125_EMIF_SDREF   0x0000093B

 #define MT41J512M8RH125_ZQ_CFG    0x50074BE4

 #define MT41J512M8RH125_RATIO    0x80

 #define MT41J512M8RH125_INVERT_CLKOUT  0x0

 #define MT41J512M8RH125_RD_DQS    0x3B

 #define MT41J512M8RH125_WR_DQS    0x3C

 #define MT41J512M8RH125_PHY_FIFO_WE   0xA5

 #define MT41J512M8RH125_PHY_WR_DATA   0x74

 #define MT41J512M8RH125_IOCTRL_VALUE  0x18B

Can you guess a cause to fail in the software leveling? If the seed values are not correct, does the software leveling fail with the incorrect result?

Best regards,

Daisuke