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Address phase problem in AM437x GPMC Sync AAD Muxed Mode

g.f.
Guru 15520 points

Hi,

I have a question about AM437x GPMC synchronous AAD Mux Mode.

I'm using sync AAD Mux Mode(16bit burst)and having a trouble in read access and write access.

At phase of Address on the A/D bus, when I check the A/D bus by oscilloscope only MSB address are sent and

LSB address was all zero which is not the address I sent. But the data which was sent after address phase, it was correct(which I sent)

I don't know the reason why LSB address was all zero.

Is there any GPMC Configuration Register 1 to 7 for sync AAD Mux Mode which I can refer to?

I want to know the GPMC Configuration Register values which is tested and both MSB and LSB address appeared on the A/D bus correctly.

By the way, if I change the GPMC_CONFIG1_0 bit[29](READTYPE) and bit[27] to "Read Asynchronous" and "Write Asynchronous",

the MSB and LSB address appeared correctly. I changed only READTYPE and WRITETYPE, other settings are the same.

best regards,

g.f.

  • 0
    Guru 15520 points
    I forgot to write the register value.
    The GPMC configuration registers are set as follows:
    GPMC_CONFIG1_0 = 0x79E51101
    GPMC_CONFIG2_0 = 0x001F1F02
    GPMC_CONFIG3_0 = 0x55090937
    GPMC_CONFIG4_0 = 0x1E0CDE3C
    GPMC_CONFIG5_0 = 0x020F1010
    GPMC_CONFGI6_0 = 0x0F0C0404
    GPMC_CONFIG7_0 = 0x00000F50 (CSVALID was set after other register setting was done)

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 393215 points

    Hi g.f,

    Do you have receiver enabled in the pinmux of GPMC_CLK?

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points

    Hi Biser,

    Thank you for the reply.

    Yes, RXACTIVE is already enabed.

    best regard,

    g.f.

  • 0 in reply to g.f.
    TI__Guru**** 393215 points

    Can you post a scope screenshot of the signal waveforms?

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points

    Hi Biser,

    I will attach the signal file.

    Best regards,

    g.f.

    AM437x GPMC SYNC AAD Mux signal.pdf

  • 0 in reply to g.f.
    TI__Guru**** 393215 points

    Hi g.f,

    What is the GPMC_CLK frequency? I seem to remember that at higher frequencies the GPMC_ADVn_ALE signal needed to be a bit longer - 2 or 3 clock periods for each address phase.

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Thank you for the reply.

    From AM437x TRM(revC) page.270 Figure 6-8 "Internal Clocking Architecture",
    I guess GPMC_FCLK = 100MHz(fixed).

    My customer are setting GPMC_CONFIG1_0 bit[1:0] = "0x1(=GPMC_FCLK/2)"
    so that GPMC_CLK should be 50MHz.

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 393215 points

    I'm attaching a document which shows AAD burst configurations for different GPMC_CLK frequencies. You can use these settings to verify your timings.

    GPMC_AAD_sync_burst_writes.pptx

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Thank you so much.
    I will share the settings to my customer.

    By the way, which device did you test with the attached settings?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 393215 points

    This has been tested on Beaglebone Black, no device attached. Problem was to get correct waveforms.

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Thank you for the reply.
    I understood. So, target was AM335x.

    AM437x GPMC is same as AM335x so that the customer can try with the setting and modify to their attached device.

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 393215 points

    Yes, this should work on AM437X too.

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Thank you so much.

    best regards,
    g.f.
  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    I have new question about GPMC AADMUX mode.

    My customer tried GPMC AADMUX mode with the setting which you attached( 50MHz version).
    By that setting ADVn was asserted/deasserted only once.
    Q1.
    In this case how to detect the 1st address phase and 2nd address phase?
    My understanding is as follows:
    ***************************************************************
    1st address : when ADVn and OEn is Low
    2nd address: when ADVn is Low and OEn is High
    So, ADVn doesn't need to be asserted twice for address phases.
    ***************************************************************
    Is it correct?

    Q2.
    In TRM(spruhl7c) page.1160 Figure 9-23 , ADVn is asserted twice.
    Is it possible to detect 1st/2nd address by ADVn rising edge in "Synchronous Multiple Read/Write (Burst Write) in Address/Address/Data-Multiplexed Mode"?

    Q3.
    In TRM(spruhl7c) page.1160 Figure 9-23 "Synchronous Multiple Write (Burst Write) in Address/Address/Data-Multiplexed Mode",
    nWE signal are asserted a few cycle during address phase.
    It seems that nWE is not asserted during data phase. Does this mean that nWE is not need to be asserted in this mode?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 393215 points

    g.f. said:
    My customer tried GPMC AADMUX mode with the setting which you attached( 50MHz version).
    By that setting ADVn was asserted/deasserted only once.

    This is not correct. Please post GPMC register settings and scope screenshots.

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points

    Hi Biser,

    Thank you for the reply.

    The GPMC register settings is as follows:

    //////////////////////////////////////////////////////

    GPMC_CONFIG1 = 0x79601101
    GPMC_CONFIG2 = 0x00100c80
    GPMC_CONFIG3 = 0x44060684
    GPMC_CONFIG4 = 0x06848c86
    GPMC_CONFIG5 = 0x020a0c0e
    GPMC_CONFIG6 = 0x0a080000
    GPMC_CONFIG7 = 0x00000f50

    //////////////////////////////////////////////////////

    By this settings, CS signal never be deasserted after GPMC read access is finished.

    I will attach the signal screenshot.

    AM437x GPMC_AADMUX.pdf

    best regards,

    g.f.

  • 0 in reply to g.f.
    TI__Guru**** 393215 points

    Please check the nADV signal with an oscilloscope. I will ask for help on this, but answers will be delayed due to holidays in the USA.

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Do you mean that ADVn should be asserted twice for 1st/2nd address phase by the attached GPMC settings?
    But the signal screenshot which you attached a few days ago, it seem that ADVn signal was asserted once.

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 393215 points

    Yes, it should pulse low twice, with nOE low on first pulse and high on second. See Figure 9-23 in the AM437X TRM Rev. C. The .ppt screenshots don't catch the entire sequence.

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Thank you for the reply.

    Yes, I know that ADVn signal was asserted low twice in Figure 9-23.
    But in Synchronous AAD Mux mode, I guess that ADVn doesn't need to be asserted twice.
    Please see page.1141 "9.1.3.3.9.3". It said as follow:
    ////////////////////////////////////////////////////////////////////////////////
    ADVAADMUXxxOFFTIME can be programmed to the same value as ADVONTIME if no high ADVn pulse
    is needed between the two AAD-mux address phases, which is the typical case in synchronous mode. In
    this configuration, ADVn is kept low until it reaches the correct ADVxxOFFTIME.
    ////////////////////////////////////////////////////////////////////////////////

    In such case(keep ADVn low), I guess 1st address can be captured by GPMC_CLK edge during ADVn and OEn are low,
    2nd address can be captured by GPMC_CLK edge during ADVn are low and OEn are High.

    By the way, is it possible to capture 1st/2nd address by ADVn rising edge in
    "Synchronous Multiple Read/Write (Burst Write) in Address/Address/Data-Multiplexed Mode"?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 393215 points
    I don't know what are the device capabilities at the other end of the GPMC.
  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Biser,
    I'm very sorry, I can't uderstand.
    Which question are you answering to?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 393215 points

    I replied to this post:

    g.f. said:
    Yes, I know that ADVn signal was asserted low twice in Figure 9-23.
    But in Synchronous AAD Mux mode, I guess that ADVn doesn't need to be asserted twice.
    Please see page.1141 "9.1.3.3.9.3". It said as follow:
    ////////////////////////////////////////////////////////////////////////////////
    ADVAADMUXxxOFFTIME can be programmed to the same value as ADVONTIME if no high ADVn pulse
    is needed between the two AAD-mux address phases, which is the typical case in synchronous mode. In
    this configuration, ADVn is kept low until it reaches the correct ADVxxOFFTIME.
    ////////////////////////////////////////////////////////////////////////////////

    In such case(keep ADVn low), I guess 1st address can be captured by GPMC_CLK edge during ADVn and OEn are low,
    2nd address can be captured by GPMC_CLK edge during ADVn are low and OEn are High.

    By the way, is it possible to capture 1st/2nd address by ADVn rising edge in
    "Synchronous Multiple Read/Write (Burst Write) in Address/Address/Data-Multiplexed Mode"?

  • 0 in reply to Biser Gatchev-XID
    TI__Guru**** 393215 points
    I have asked the factory team to help on this, by the way, but reply from there will be delayed due to holidays in the USA.
  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Thank you so much for always supporting me.
    Okay, I will wait for the reply.

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru* 86180 points
    Hi gf,
    i read thru the posts, but I'm a little confused on what the issue is:

    Do you still have the problem that CS0 is not deasserting?
    Do you still have the problem that the LS address word is all zeros?

    Your best guide would be Figure 7-23 in the TRM. Ensure all signals conform to these timings. Please attache scope shots if they don't.

    regards,
    James
  • 0 in reply to JJD
    Guru 15520 points

    Hi James,

    Thank you for the reply.

    Please look at the attached file which I attached a few weeks ago.

    The address part looks fine but CS0 are asserted continously.

    Also OE singlal are asserted continously.

    The GPMC are configured as Multiple read/write access.

    But customer tried only one single read access for this time.

    Question1:

    In this case, does CS0 will be asserted continously until the next access?

    I also have question about the AM437x TRM(spruhl7c) page.1160 Figure 9-23.

    In the Figure, the timing of nADV seems typo.

    The timing is written as OEAADMUXOFFTIME and OEAADMUXONTIME.

    Question2:

    I guess it should be ADVAADMUXWROFFTIME and ADVAADMUXWRONTIME, isn't it?

    And I'm confused about the timing of nWE.

    nWE is deasserted before the data phase.

    Question3:

    Is this timing correct for nWE?

    6036.AM437x GPMC_AADMUX.pdf

    best regards,

    g.f.

  • 0 in reply to g.f.
    TI__Guru* 86180 points
    gf, can you send the CONFIG1-7 registers of the chip select you are using? This will help me explain the timing you are seeing.

    It looks like you might be trying to operate the interface at 100MHz. I would suggest slowing the interface down (using GPMCFCLKDIVIDER=4) to 25MHz to get functional before trying to optimize for faster speeds.

    The fact that CS0 is asserted continuously means that the cycle is not completing. The GPMC controller may be missing some clock edges in its state machine at 100MHz, so changing to 25MHz may help this. CS should deassert depending on CSRDOFFTIME (or CSWROFFTIME if you are doing a write)

    For AAD mode there are 2 address cycles, and the timing of the first nADV pulse is dictated by OEAADMUXOFFTIME/OEAADMUXONTIME, and the second is dictated by ADVRDOFFTIME/ADVONTIME (ADVWROFFTIME for writes). You have to ensure all of these timings don't overlap in your configuration, otherwise the GPMC controller will get confused.

    The nWE signal pulse is correct. The signal is valid during data phase, and the clock is used to clock in/out the data. I believe this could change depending on the requirements of the device you are talking to.

    Regards,
    James
  • 0 in reply to JJD
    Guru 15520 points
    Hi James,

    Thank you for the reply.

    The customer tried following CONFIG1-7 register values:
    ////////////////////////////
    GPMC_CONFIG1 = 0x79601101
    GPMC_CONFIG2 = 0x00100c80
    GPMC_CONFIG3 = 0x44060684
    GPMC_CONFIG4 = 0x06848c86
    GPMC_CONFIG5 = 0x020a0c0e
    GPMC_CONFIG6 = 0x0a080000
    GPMC_CONFIG7 = 0x00000f50
    ////////////////////////////

    They are using GPMCFCLKDIVIDER=01b(GPMC_CLK/2), so it is 50MHz.

    By the way, I'm confused about the nADV dictation.
    I thought first nADV pulse will be dictated by ADVAADMUXONTIME/ADVAADMUXOFFTIME,
    and the second will be dictated by ADVRDOFFTIME/ADVONTIME(ADVWROFFTIME for writes).
    Is this wrong?

    Isn't OEAADMUXOFFTIME/OEAADMUXONTIME for first OE assertion/deassertion
    and OEOFFTIME/OEONTIME for second OE assertion/deassertion(for read transaction)?
    So, I guess there are typo in Figure 9-23 of AM437x TRM(revC)page.1160,
    OEAADMUXOFFTIME/OEAADMUXONTIME are written against both nADV and nOE signal.

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru* 86180 points
    Hi gf, you are correct on the typos in the figure. I will get that corrected in the TRM.

    A few thing to try on your GPMC_CONFIG registers:
    -set all the EXTRADELAY bits to 0. The CS0 in the timing diagram is off by half a clock cycle, and i think the EXTRADELAY setting is the problem. Setting all EXTRADELAY=0 will help line up CSn0 with the beginning of the GPMC_CLK
    -you have the first address cycle (dictated by ADVAADMUXON and ADVAADMUXOFF) with a width of 4 clock cycles, but the second address cycle (dictated by ADVONTIME and ADVWROFFTIME) is only a width of 2 cycles. Try making these both 4 clock cycles by setting ADVWROFFTIME=8.
    -Also change WEONTIME and WEOFFTIME to line up with the ADVON/OFF time changes above.

    I think if you keep the rest of the parameters the same, you should see a difference. If you can send the timing diagram and a dump of the registers after these changes, i can help further.

    Regards,
    James
  • 0 in reply to JJD
    Guru 15520 points
    Hi James,

    Thank you for the reply.

    Okay, I will tell my customer to change the all EXTRADELAY=0,
    and ADVWROFFTIME=8, WEOFFTIME=8 to line up with the ADVON/OFF time changes.

    But before telling to the customer, I have following question.

    Does ADVRDOFFTIME and OEONTIME need to be changed?
    To line up with the ADVON/OFF time, I guess ADVRDOFFTIME and OEONTIME also need to be changed as follow:
    ADVRDOFFTIME = 8
    OEONTIME = 8

    best regards,
    g.f.
  • 0 in reply to JJD
    Guru 15520 points
    Hi James,

    I have additional question.

    In AM437x TRM(spruhl7c) page.1160 Figure 9-23
    "Synchronous Multiple(Burst Write) in Address/Address/Data Multiplexed Mode",
    nADV signal are asserted twice for first and second address phase.

    Right now, the ADVAADMUXWROFFTIME/ADVAADMUXRDOFFTIME and ADVONTIME are set to 4,
    so that nADV signal are asserted once(keeping low after first address phase).
    But my customer want to assert nADv signal twice as Figure 9-23.
    And they want to know the all GPMC_CONFIG register values for this case.
    Is there any register value which they can refer to? Or can you give me an advise?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru* 86180 points

    Hi g.f,

    you will get 1 pulse if the OFF time of the first cycle is the same as the ON time of the second cycle.  So if they want 2 cycles, they will have to set, for example, ADVAADMUXWROFFTIME=4 and ADVONTIME=6.

    Regards,

    James

  • 0 in reply to JJD
    Guru 15520 points
    Hi James,

    Thank you for the reply and sorry for the delay, I was out of office last week.

    I understood how to get 2 pulse.
    By the way, your attached example seems that 2 cycle are added to ADVONTIME which value suggested at previous post.
    Do I also need to add 2 cycle to other parameter?
    For example,
    ADVWROFFTIME=8 => ADVWROFFTIME=10
    WRDATAONADMUXBUS=8 => WRDATAONADMUXBUS=10
    WEONTIME=4 => WEONTIME=6 (same cycle with ADVONTIME)
    WEOFFTIME=8 => WEOFFTIME=10

    best regards,
    g.f.