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C6713B PLLCSR Reserved Bits 2 and 5 are set

Matthew Hedrick
Prodigy 40 points

I am bringing up a custom board with the C6713B processor. When trying to configure and enable the PLL my target gets lost and try to execute from a random location right after I try to enable the PLL. When looking from the memory browser I can see that after I attempt to enable the PLL the settings go back to the defaults. Occassionally instead of going back to the defaults I receive a value of 0x64 or 0x60 for PLLCSR. The data sheet shows bits 2 and 5 as reserved but the thread included below says these relate to the status of the PLL. Can I get a summary of what bits 2, 4, and 5 represent? My PLL settings work on the DSK6713 so it shouldn't be my code. The electronics team left out the EMI filter on the PLLHV. Could this be related?

https://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/p/143068/529283

Thanks

  • 0
    TI__Mastermind 43660 points
    Hello Matthew,

    From the thread you referred above, i understand the reserved bit is meant for PLL lock. I believe the PLL lock is not happened in your custom board and cause this issue.

    The EMI filter and capacitors are well recommended for PLLHV. Did you ensure your input clock signal quality and its transition time <=5ns ?

    what is the difference between the DSK6713 and your custom board ?

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 40 points
    Thanks for the reply. We have verified the clock quality. I am not able to identify any differences between the the DSK and my board that would effect PLL other than the EMI filter.

    I believe Bit 5 shows lock but what does bit 4 and bit 2 represent? Since I have seen bit 2 set as 1 I am very interested in that. Also, what could cause PLL to be stable, locked, but not enabled after attempting to enable it?

    Thanks again.
  • 0 in reply to Matthew Hedrick
    TI__Mastermind 43660 points
    Matthew,

    I will have to investigate the field description for bit 4 and bit 2. I will update you soon.

    Regards,
    Senthil