Hi All.
We are using DM8148 custom board with external MAX24287 PHY. We use RGMII0 and RGMII1 with a different phy on each end. We currently have an issue with 10mbps speed.
The communication works fine in 1000 and 100 speeds (both half and full duplex). We issue a loopback in the phy, and we using pktgen kernel module to test the interfaces. On speeds 1000 and 100 we send 10000 packets each time and it reflects as 10000 txgoodframes and 10000 rxgoodframes in the cpsw statistics.
When we lower the speed to 10mbps and send the 10000 packets, we see 10000 txcarriersenseerrors and no rxgoodframes at all.
Touching with a scope in the tx and rx lines (when loopback is on) we see data streaming from MAC to PHY (tx data) but nothing at all on rx data lines
We have tried to investigate the issue and we came to this result:
At speeds of 1000 and 100 mbps, we can see that the RGMII0_TXCTL is asserted before each sending of a packet.
At the speed of 10 mbps this line is never asserted (stays low at all times).
We have tried to leave this line in high impedance, and as a result of this action the rx line had started working in 10mbps (we saw the packets from tx lines looped back to the rx lines). But after few second we get a kernel panic of Transmit Queue 0 timed out (makes sense because RGMII0_TXCTL is never de-asserted).
Why can it be happening? Why is the RGMII0_TXCTL is not asserted by the processor only when operating at 10mbps speed?
Here are some configurations:
MACCONTROL REGISTER:
Speed 1000 - 0xa1 - (BITS 7+5+1)
Speed 100 - 0x8021 (BITS 15+5+1)
Speed 10 - 0x40021 (BITS 18+5+1)
kernel configuration has CONFIG_TI_CPSW_DUAL_EMAC
Please Help
Kind Regards :)
