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Hi. I'm new to the TI-DSP-World.
I want to move Data (50 Bits) to an FPGA (Spartan 6) via EMIFA cyclic without EDMA. I want to trigger the data transfer over a timer interrupt every 5us. I'm using the c6455 single core DSP. First I want to deal with the EMIFA to get a connection to the FPGA. It is not necessary to get data from the FPGA.
I want to use the CSL functions and macros.
Is there some example code to get startet with the EMIF?
Hello!
Your task breaks in two: 1) interface configuration; 2) data exchange. The latter one is trivial when the former is done. EMIF has an address window, accesses to which are translated into bus cycles on the interface. So from program perspective you do loads and stores of data to EMIF's address. You may want to look at something like CONTENTS_OF macro and probably adjust to your needs, e.g. give some friendly name. So in you code that might look just like FPGA_WRITE( foo );
However, before you get there, a lot of preparation work should be done. First of all, you have to configure your EMIF in desired mode. Asynchronous memory interface with programmable phases is an easiest to my understanding. I could share some examples just to give you idea how that looks like, but mine device was C6414, so you'll have to change a lot.
Another big issue is FPGA side. You better talk to you FPGA designer if that's not you. You also may want to read this appnote .
Hello, Patrick,
As mine experience was with different processor and library version, I would refrain giving you direct instructions. However, you may find a good example made by TI. As long as you able to deal with CSL, I suppose you have it installed already, but just in case, refer .
Inside those deliverable please find 03.00.10.02\6455\default_package\csl_c6455\example\emifa\src\Emifa_ReadWrite_example.c It will give you idea how to deal with the interface setup.
As to the last question, again, you will find the reference in the mentioned example, here let me give you just basic idea. First, refer to the data manual on your device Table 2-2 with memory map.
It tells EMIFA CE2 A000 0000 - A07F FFFF. In other words, whenever you try to write something at address withing that window, EMIFA will execute write cycle on the bus, if you are truing to read something from that window - the bus will take read cycle. So if you have something like unsigned *pdata = (unsigned *)0xA0000000, then pdata[0] = foo; will issue write cycle, and value on the data bus would be foo. If you try bar = pdata[1]; then EMIF will execute read cycle and load to bar value of the word with offset one, that is address bus would have word address 1.
Next I suggest to refer . There you will find description of data bus, address bus and control signal names, as well as timing diagrams of the access cycles.
