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AM437x DDR PHY Register configuration

g.f.
Guru 15510 points 
Hi,

My customer are having problem with AM437x DDR3.
Their layout of DDR3 are followed by AM437x Datasheet layout guideline
and it ssems fine.

I have questions about DDR PHY Registers of AM437x.
As following TI wiki page said to refer to GEL of EVM, 
my customer are configuring the value of  DDR PHY registers as follow:
processors.wiki.ti.com/.../AM437x_DDR_Configuration_and_Programming_Guide

We refer to the GEL file which can be download from following TI Web page.
processors.wiki.ti.com/.../File:AM437x_GELs.zip
*EMIF4D_EXT_PHY_CTRL_26-EMIF4D_EXT_PHY_CTRL_30
Setting "0x20" to each bit[26:16] and bit[10:0] Ratio(Gate Leveling init ratio 0-9)

*EMIF4D_EXT_PHY_CTRL_31-EMIF4D_EXT_PHY_CTRL_35
Setting "0x00" to each register bit[21:16] and bit[5:0] Ratio(Write Leveling init ratio 0-9)

Q1.
Does this register's value of GEL depend to the layout length?
Or is the value of GEL applicable to every kind of layout length?

Q2.
How to detect Full leveling are done successfully?
In GEL file of EVM, it is waiting for EMIF4D_READ_WRITE_LEVELING_CTRL bit[31]
"RDWRLVLFULL_START" to be zero for completion of leveling.
If this bit are cleared, does it mean that leveling are done successfully?

Q3.
Or does user should check EMIF4D_STS bit[6:4] and above "RDWRLVLFULL_START"bit together
to find out the leveling are done successfully?

best regards,
g.f.
  • 0
    TI__Guru**** 393215 points
    Hi,

    I will forward this to the DDR experts.
  • 0 in reply to Biser Gatchev-XID
    Guru 15510 points
    Hi Biser,

    Thank you for the reply.

    Sorry, but I have additional question about AM437x DDR3.

    It seems there are two types of GEL file for DDR3 initialization.
    One is which do software leveling and other do hardware leveling.
    The software leveling GEL file are included in CCS folder and
    the hardware leveling GEL file can be downloaded from following wiki page.
    processors.wiki.ti.com/.../File:AM437x_GELs.zip

    Why there are two types of GEL file?
    Are there any reason for this?

    Our customer are having DDR3 write access problem as following:
    ********************************************************************************
    Two 16bit DDR3L(128M) as 32bit banks are on the board.
    When write leveling are enabled, there are problem of write access against upper 16bit DDR3L.
    It can't access successfully. But it can write access against lower 16bit DDR3L successfully.
    ********************************************************************************
    So, the answer for the question may be a hint for the problem.

    By the way, their layout are followed to the AM437x datasheet guidline.

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Genius 9655 points

    HW leveling is the supported option for AM437x DDR interface and you can find the relevant GEL files as you noted in the link below:

    http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM437x

     Without more details on the actual error and details, it would be very hard to debug this issue. Do you have a simple GEL file that you can point to us with details on how the SDRAM timing registers, configuration registers are setup?

    Regards, Siva

  • 0 in reply to sivak
    Guru 15510 points
    Hi Siva,

    Thank you for the reply.

    I will ask to my customer to give us their GEL file.

    But could you please answer to the following questions which I posted previously?
    ////////////////////////////////////////////////////////////////////////////////
    *EMIF4D_EXT_PHY_CTRL_31-EMIF4D_EXT_PHY_CTRL_35
    Setting "0x00" to each register bit[21:16] and bit[5:0] Ratio(Write Leveling init ratio 0-9)

    Q1.
    Does this register's value of GEL depend to the layout length?
    Or is the value of GEL applicable to every kind of layout length?

    Q2.
    How to detect Full leveling are done successfully?
    In GEL file of EVM, it is waiting for EMIF4D_READ_WRITE_LEVELING_CTRL bit[31]
    "RDWRLVLFULL_START" to be zero for completion of leveling.
    If this bit are cleared, does it mean that leveling are done successfully?

    Q3.
    Or does user should check EMIF4D_STS bit[6:4] and above "RDWRLVLFULL_START"bit together
    to find out the leveling are done successfully?

    Q4.
    It seems there are two types of GEL file for DDR3 initialization.
    One is which do software leveling and other do hardware leveling.
    The software leveling GEL file are included in CCS folder and
    the hardware leveling GEL file can be downloaded from following wiki page.
    processors.wiki.ti.com/.../File:AM437x_GELs.zip

    Why there are two types of GEL file?
    Are there any reason for this?

    Best regards,
    g.f.
  • 0 in reply to sivak
    Guru 15510 points 
    Hi Siva,

We got the source code of EMIF initialization.
It is customer source code so that I should not attach to this forum.
But I will attach the file of SDRAM timing register and SDRAM config register value.
Please take a look.

best regards,
g.f.

    AM437x DDR3 Register Value.xlsx

  • 0 in reply to g.f.
    TI__Genius 9655 points

    Q1.
    Does this register's value of GEL depend to the layout length?
    Or is the value of GEL applicable to every kind of layout length?

    SIVA>> The value in GEL file should work for different layouts

    Q2.
    How to detect Full leveling are done successfully?
    In GEL file of EVM, it is waiting for EMIF4D_READ_WRITE_LEVELING_CTRL bit[31]
    "RDWRLVLFULL_START" to be zero for completion of leveling.
    If this bit are cleared, does it mean that leveling are done successfully?

    Q3.
    Or does user should check EMIF4D_STS bit[6:4] and above "RDWRLVLFULL_START"bit together
    to find out the leveling are done successfully?

    SIVA>> As is done in the GEL file, EMIF4D_STS bits should be checked for any errors after the leveling start bit is cleared.


     Q4.
    It seems there are two types of GEL file for DDR3 initialization.
    One is which do software leveling and other do hardware leveling.
    The software leveling GEL file are included in CCS folder and
    the hardware leveling GEL file can be downloaded from following wiki page.
    processors.wiki.ti.com/.../File:AM437x_GELs.zip

    Why there are two types of GEL file?
    Are there any reason for this?

    SIVA>> The SW leveling GEL file was during the initial development where we were still validating HW leveling. There are no special usage restrictions that limit usage of one vs. other. As I said earlier, we suggest that you use the latest GEL files that use HW leveling.


    We also received additional information from the TI FAE and we're investigating the report and will provide additional feedback

    Regards, Siva