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66AK2H12 custom board DDR3 issues

suresh subramanium
Prodigy 220 points
Other Parts Discussed in Thread: 66AK2H14, UCD9244, UCD9090, 66AK2H12

 Hi

We are developing a PCB based on the 66AK2h14/12/06 (keystone 2) processor rev 2.0 that is similar to EVMK2H.  We are having issues in bringing up the DDR2 SODIMM (DDR3A) and DDR3B interfaces.  On debug, we can see both interfaces are behaving in the similar fashion.  Here is the summary of debug.  We can see 100 MHZ clock supplies to SOC (66AK2h14/12/06 )for both DDR3A controller and DDR3B controller are good that is we can see in scope in the input of the SOC is of 100 MHZ frequency and 0.78 V P-P.  We are using the same initialization code as provided by TI for EVMK2H that we are running in no boot mode via JTAG emulator.  We can see that PLL is get locked but we do not see any clocks coming out of the SoC DDR interfaces and reset remain asserted ~(0 V).  We also check the PDSTAT and MDSTAT they are both giving values as 0x301 and 0x10F3, respectively.  They seems to be good to us.

Can you please provide us help to figure out why we are not seeing clocks in scope coming out of the DDR interfaces when we think that input DDR’s clocks are good and PLL is locked?

BR

Suresh

  • 0
    TI__Mastermind 43660 points
    Suresh,

    Did you check the DDR voltage source and device reset ? What is the DDR PLL configurations ?

    Please run the DDR3 debug gel file in below link and share the log.

    www.ti.com/.../sprac04

    Regards,
    Senthil
  • 0
    TI__Guru* 81335 points

    Hi Suresh,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

  • 0 in reply to Raja
    TI__Mastermind 46460 points

    We only support DDR3 SDRAM topologies.  Hopefully this statement is a typo:

    "DDR2 SODIMM (DDR3A) and DDR3B interfaces"

    The DDR3 configuration contained in the EVMK2H software will not work with your board.  You must adjust this configuration to match your SDRAM timing and topology.  Please review the KS2 DDR3 Controller UG (SPRUHN7) and the KS2 DDR3 Init Guide (SPRABX7) with associated REG_CALC spreadsheet and the KS DDR3 Layout Guide (SPRABI1).

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points

    Thanks

    Why it won't work for our topology?  We are using same part number for sdram as used in evmk2h. and for so_dimm we are using same ram card that was shipped with evmk2h. I am attaching out put of ddr3_debug.gel. I encountered errors at leveling.

    config_good.txt
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    C66xx_0: GEL Output: ****************************************************************************************************************
    C66xx_0: GEL Output: ********************************************************
    C66xx_0: GEL Output: DDR PLL Registers:
    C66xx_0: GEL Output: DDR3A_PLL_CTL0 register: 0x092804C0 (0x02620360)
    C66xx_0: GEL Output: PLLD[5:0]: 0 (Pre-Divide value of 1)
    C66xx_0: GEL Output: PLLM[18:6]: 19 (Multiplier value of 20)
    C66xx_0: GEL Output: CLKOD[22:19]: 5 (Output Divide value of 6)
    C66xx_0: GEL Output: BYPASS[23]: 0
    C66xx_0: GEL Output: BWADJ-lower[31:24]: 9
    C66xx_0: GEL Output: DDR3A_PLL_CTL1 register: 0x00000040
    C66xx_0: GEL Output: PLLRESET[14]: Reset ** DEASSERTED ** to PLL
    C66xx_0: GEL Output: ENSAT[6]: ENSAT is SET - (GOOD)
    C66xx_0: GEL Output: BWADJ-upper[3:0]: 0
    C66xx_0: GEL Output: BWADJ[11:0] (combined): 9
    C66xx_0: GEL Output: ****************************************************************************************************************
    C66xx_0: GEL Output: ****************************************************************************************************************
    C66xx_0: GEL Output: ********************************************************
    C66xx_0: GEL Output: DDR PLL Registers:
    C66xx_0: GEL Output: DDR3A_PLL_CTL0 register: 0x092804C0 (0x02620360)
    C66xx_0: GEL Output: PLLD[5:0]: 0 (Pre-Divide value of 1)
    C66xx_0: GEL Output: PLLM[18:6]: 19 (Multiplier value of 20)
    C66xx_0: GEL Output: CLKOD[22:19]: 5 (Output Divide value of 6)
    C66xx_0: GEL Output: BYPASS[23]: 0
    C66xx_0: GEL Output: BWADJ-lower[31:24]: 9
    C66xx_0: GEL Output: DDR3A_PLL_CTL1 register: 0x00000040
    C66xx_0: GEL Output: PLLRESET[14]: Reset ** DEASSERTED ** to PLL
    C66xx_0: GEL Output: ENSAT[6]: ENSAT is SET - (GOOD)
    C66xx_0: GEL Output: BWADJ-upper[3:0]: 0
    C66xx_0: GEL Output: BWADJ[11:0] (combined): 9
    C66xx_0: GEL Output: ****************************************************************************************************************
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    ddr3A_levling_1.txt
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    ddr3A_levling_1
    C66xx_0: GEL Output: ****************************************************************************************************************
    C66xx_0: GEL Output: ***************** DDR3B Leveling Errors *********************
    C66xx_0: GEL Output: PGSR0[27]: WEERR has ** No Error **
    C66xx_0: GEL Output: PGSR0[26]: REERR has ** No Error **
    C66xx_0: GEL Output: PGSR0[25]: WDERR has ** No Error **
    C66xx_0: GEL Output: PGSR0[24]: RDERR has ** Error **
    C66xx_0: GEL Output: PGSR0[23]: WLAERR has ** Error **
    C66xx_0: GEL Output: PGSR0[22]: QSGERR has ** Error **
    C66xx_0: GEL Output: PGSR0[21]: WLERR has ** Error **
    C66xx_0: GEL Output: PGSR0[20]: ZCERR has ** Error **
    C66xx_0: GEL Output: PGSR0[11]: WEDONE is ** Not Set **
    C66xx_0: GEL Output: PGSR0[10]: REDONE is ** Not Set **
    C66xx_0: GEL Output: PGSR0[9]: WDDONE is ** Not Set **
    C66xx_0: GEL Output: PGSR0[8]: RDDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[7]: WLADONE is ** Set **
    C66xx_0: GEL Output: PGSR0[6]: QSGDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[5]: WLDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[4]: DIDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[3]: ZCDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[2]: DCDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[1]: PLDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[0]: IDONE is ** Set **
    C66xx_0: GEL Output: ********************************************************
    C66xx_0: GEL Output: Leveling Errors by Byte Lane:
    C66xx_0: GEL Output: Byte Lane 0:
    C66xx_0: GEL Output: DX0GSR2[6]: WEERR has ** No Error **
    C66xx_0: GEL Output: DX0GSR2[4]: REERR has ** No Error **
    C66xx_0: GEL Output: DX0GSR2[2]: WDERR has ** No Error **
    C66xx_0: GEL Output: DX0GSR2[0]: RDERR has ** Error **
    C66xx_0: GEL Output: DX0GSR0[25]: QSGERR on Rank1 has ** No Error **
    C66xx_0: GEL Output: DX0GSR0[24]: QSGERR on Rank0 has ** Error **
    C66xx_0: GEL Output: DX0GSR0[6]: WLERR has ** Error **
    C66xx_0: GEL Output: Byte Lane 1:
    C66xx_0: GEL Output: DX1GSR2[6]: WEERR has ** No Error **
    C66xx_0: GEL Output: DX1GSR2[4]: REERR has ** No Error **
    C66xx_0: GEL Output: DX1GSR2[2]: WDERR has ** No Error **
    C66xx_0: GEL Output: DX1GSR2[0]: RDERR has ** Error **
    C66xx_0: GEL Output: DX1GSR0[25]: QSGERR on Rank1 has ** No Error **
    C66xx_0: GEL Output: DX1GSR0[24]: QSGERR on Rank0 has ** Error **
    C66xx_0: GEL Output: DX1GSR0[6]: WLERR has ** Error **
    C66xx_0: GEL Output: Byte Lane 2:
    C66xx_0: GEL Output: DX2GSR2[6]: WEERR has ** No Error **
    C66xx_0: GEL Output: DX2GSR2[4]: REERR has ** No Error **
    C66xx_0: GEL Output: DX2GSR2[2]: WDERR has ** No Error **
    C66xx_0: GEL Output: DX2GSR2[0]: RDERR has ** Error **
    C66xx_0: GEL Output: DX2GSR0[25]: QSGERR on Rank1 has ** No Error **
    C66xx_0: GEL Output: DX2GSR0[24]: QSGERR on Rank0 has ** Error **
    C66xx_0: GEL Output: DX2GSR0[6]: WLERR has ** Error **
    C66xx_0: GEL Output: Byte Lane 3:
    C66xx_0: GEL Output: DX3GSR2[6]: WEERR has ** No Error **
    C66xx_0: GEL Output: DX3GSR2[4]: REERR has ** No Error **
    C66xx_0: GEL Output: DX3GSR2[2]: WDERR has ** No Error **
    C66xx_0: GEL Output: DX3GSR2[0]: RDERR has ** Error **
    C66xx_0: GEL Output: DX3GSR0[25]: QSGERR on Rank1 has ** No Error **
    C66xx_0: GEL Output: DX3GSR0[24]: QSGERR on Rank0 has ** Error **
    C66xx_0: GEL Output: DX3GSR0[6]: WLERR has ** Error **
    C66xx_0: GEL Output: Byte Lane 4:
    C66xx_0: GEL Output: DX4GSR2[6]: WEERR has ** No Error **
    C66xx_0: GEL Output: DX4GSR2[4]: REERR has ** No Error **
    C66xx_0: GEL Output: DX4GSR2[2]: WDERR has ** No Error **
    C66xx_0: GEL Output: DX4GSR2[0]: RDERR has ** Error **
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    ddr3B_levling_1.txt
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    ddr3B_levling_1
    C66xx_0: GEL Output: ****************************************************************************************************************
    C66xx_0: GEL Output: ***************** DDR3B Leveling Errors *********************
    C66xx_0: GEL Output: PGSR0[27]: WEERR has ** No Error **
    C66xx_0: GEL Output: PGSR0[26]: REERR has ** No Error **
    C66xx_0: GEL Output: PGSR0[25]: WDERR has ** No Error **
    C66xx_0: GEL Output: PGSR0[24]: RDERR has ** Error **
    C66xx_0: GEL Output: PGSR0[23]: WLAERR has ** Error **
    C66xx_0: GEL Output: PGSR0[22]: QSGERR has ** Error **
    C66xx_0: GEL Output: PGSR0[21]: WLERR has ** Error **
    C66xx_0: GEL Output: PGSR0[20]: ZCERR has ** Error **
    C66xx_0: GEL Output: PGSR0[11]: WEDONE is ** Not Set **
    C66xx_0: GEL Output: PGSR0[10]: REDONE is ** Not Set **
    C66xx_0: GEL Output: PGSR0[9]: WDDONE is ** Not Set **
    C66xx_0: GEL Output: PGSR0[8]: RDDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[7]: WLADONE is ** Set **
    C66xx_0: GEL Output: PGSR0[6]: QSGDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[5]: WLDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[4]: DIDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[3]: ZCDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[2]: DCDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[1]: PLDONE is ** Set **
    C66xx_0: GEL Output: PGSR0[0]: IDONE is ** Set **
    C66xx_0: GEL Output: ********************************************************
    C66xx_0: GEL Output: Leveling Errors by Byte Lane:
    C66xx_0: GEL Output: Byte Lane 0:
    C66xx_0: GEL Output: DX0GSR2[6]: WEERR has ** No Error **
    C66xx_0: GEL Output: DX0GSR2[4]: REERR has ** No Error **
    C66xx_0: GEL Output: DX0GSR2[2]: WDERR has ** No Error **
    C66xx_0: GEL Output: DX0GSR2[0]: RDERR has ** Error **
    C66xx_0: GEL Output: DX0GSR0[25]: QSGERR on Rank1 has ** No Error **
    C66xx_0: GEL Output: DX0GSR0[24]: QSGERR on Rank0 has ** Error **
    C66xx_0: GEL Output: DX0GSR0[6]: WLERR has ** Error **
    C66xx_0: GEL Output: Byte Lane 1:
    C66xx_0: GEL Output: DX1GSR2[6]: WEERR has ** No Error **
    C66xx_0: GEL Output: DX1GSR2[4]: REERR has ** No Error **
    C66xx_0: GEL Output: DX1GSR2[2]: WDERR has ** No Error **
    C66xx_0: GEL Output: DX1GSR2[0]: RDERR has ** Error **
    C66xx_0: GEL Output: DX1GSR0[25]: QSGERR on Rank1 has ** No Error **
    C66xx_0: GEL Output: DX1GSR0[24]: QSGERR on Rank0 has ** Error **
    C66xx_0: GEL Output: DX1GSR0[6]: WLERR has ** Error **
    C66xx_0: GEL Output: Byte Lane 2:
    C66xx_0: GEL Output: DX2GSR2[6]: WEERR has ** No Error **
    C66xx_0: GEL Output: DX2GSR2[4]: REERR has ** No Error **
    C66xx_0: GEL Output: DX2GSR2[2]: WDERR has ** No Error **
    C66xx_0: GEL Output: DX2GSR2[0]: RDERR has ** Error **
    C66xx_0: GEL Output: DX2GSR0[25]: QSGERR on Rank1 has ** No Error **
    C66xx_0: GEL Output: DX2GSR0[24]: QSGERR on Rank0 has ** Error **
    C66xx_0: GEL Output: DX2GSR0[6]: WLERR has ** Error **
    C66xx_0: GEL Output: Byte Lane 3:
    C66xx_0: GEL Output: DX3GSR2[6]: WEERR has ** No Error **
    C66xx_0: GEL Output: DX3GSR2[4]: REERR has ** No Error **
    C66xx_0: GEL Output: DX3GSR2[2]: WDERR has ** No Error **
    C66xx_0: GEL Output: DX3GSR2[0]: RDERR has ** Error **
    C66xx_0: GEL Output: DX3GSR0[25]: QSGERR on Rank1 has ** No Error **
    C66xx_0: GEL Output: DX3GSR0[24]: QSGERR on Rank0 has ** Error **
    C66xx_0: GEL Output: DX3GSR0[6]: WLERR has ** Error **
    C66xx_0: GEL Output: Byte Lane 4:
    C66xx_0: GEL Output: DX4GSR2[6]: WEERR has ** No Error **
    C66xx_0: GEL Output: DX4GSR2[4]: REERR has ** No Error **
    C66xx_0: GEL Output: DX4GSR2[2]: WDERR has ** No Error **
    C66xx_0: GEL Output: DX4GSR2[0]: RDERR has ** Error **
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to suresh subramanium
    TI__Mastermind 46460 points

    Suresh,

    Did you copy the PCB layer stack-up and trace routing from the EVM?  Alternately, can you provide a report showing that the length matching rules have been met?

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points

    yes we copied the exact schematic for all the parts from evmk2h schematic. Moreover we are not able to see the clock output from soc to ddr3a and ddr3b. Also reset is always asserted i.e Voltage at both ends of R470 is always 0.
    I will provide the reports that you asked for by evening.

  • 0 in reply to suresh subramanium
    TI__Mastermind 46460 points

    Suresh,

    I did not ask whether you had copied the schematic.  I asked whether you had copied the routed tracks on the EVM PCB.  There is a big difference.  DDR3 layouts require significant effort and expertise.

    Your 1st post indicated complete system failure.  I thought your later post indicated that you had made progress.  I see from your last post that you still have complete system failure.  Have you verified that all supply voltages and input clocks are valid?  Have you verified that the power, clocks and reset sequencing defined in the data manual have been met?  Are you able to connect with an emulator and use CCS?  Can you build, load and run a program in on-chip memory?

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points
    Thanks tom,

    Yes I have checked all input clocks. they are fine. I have checked the sequence with Fusion USB software. All power rails have voltages as required. Also we are able to connect with emulator and use CCS. We have successfully ran Platformtest (example project in PDK_DIR). Test has detected all the interfaces (leds, uart, SGMI, eeprom, flash). it also passed the internal memory test. But stuck at external memory test.
    Together this data indicates only issue is in DDR3. The big reason of worry is that I am seeing no clock at SOC output. Even though I had bypassed the PLL by editing some registers value in xtcievmk2k.gel script.
    Pardon my knowledge about layout. I will update the status as soon as I get it from layout guy.
  • 0 in reply to suresh subramanium
    TI__Mastermind 46460 points

    Suresh,

    Please verify the power supply voltage and sequencing with a scope and voltmeter.  The information from the Fusion software is only correct if the configurations are correct.  Please also verify the clock inputs with a scope.  You should always get a DDRCLKOUT signal and the DDRRESET should toggle during SDRAM initialization.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points

    Thanks Tom,

    I talked to layout guy and he confirmed that we are using same PCB layer stack-up as in EVM.

    The power up configuration files for UCD9090 and UCD9244 are downloaded from www2.advantech.com/.../EVMK2HX_sd4.aspx. Which are exactly same as in EVM (we have compared all the parameters for both boards EVMK2H and our custom board).

    While bringing up the power for the custom board, the only change we made is to bypass VCC2V5 (Ethernet PHY power rail). We also removed dependency of Vcc2V5 from all other rails i.e. Main power good, UCD enables etc. As we were getting OV fault on this supply and we believe that the power supply is only used for the Ethernet chip.


    We checked this edited (VCC2V5 bypass) configuration with EVMK2H board and we face no issues regarding bringing power on EVMK2H. Similarly, we are not facing power issues in our custom board with this edited(i.e. bypass Vcc2V5) configuration of UCD9090. As I mentioned earlier that we are able to run example projects on SoC and specifically we ran platform test that passed all tests except external memory test. It appears to me that power is fine but if there is something missing, please let us know .

    We are looking for specific help for the input DDRCLK that we provide from pins (A25, B25) that goes inside the SOC and comes out of the DDR interface as DDRCLKOUT (A12, B12) is dependent on reset, for example, such as PLL/DDL used inside the 66AK2H12 SOC has any dependency on the reset?

    Secondly, what are the dependency for the DDR3ARESET (B14) and DDR3BRESET inside 66AK2H12, for example, such as any register bit and/or external, reset pins dependency such PORz, RESET and any other dependency.

    Please let me know, if you need any clarity about it. Thanks 

  • 0 in reply to suresh subramanium
    TI__Mastermind 46460 points

    Suresh,

    As I said before, the DDRCLKOUT should always be there even if the PLL programming is in BYPASS.  I think you need to look at more fundamental issues.  You have checked the supplies.  Have you specifically verified DDR3AVREFSSTL on pin G14 and the DVDD15 voltage on those pins.  I recommend that you make some measurements right at the vias going up to the balls to make sure the power is getting to the BGA pins.  I also suggest that you perform a new 100% check of your schematic symbol to make sure no error has been made.

    To verify your initialization software, I recommend that you run the code for your custom board directly on the EVM.  If you see a problem, then the software needs to be debugged.  If it works, even partially, on the EVM then we know there is a physical problem with your board.

    How many boards have you built and assembled?  Do they all work and fail exactly the same way?

    Please provide a report showing that the length matching rules have been met.  The layout tool should be able to generate this.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points
    Thanks Tom,
    Your cooperation is very helpful.
    Sorry for late reply as i went for checking some points that you mentioned earlier.
    Summary of my findings are:

    1- All power supplies are good except VCC2V5. VCC2v5 reports ~1.16 V all the time
    2- performed schematic symbol check. it reports no issue there.
    3- Checked Vias to VCC1V5 . All supplies are good.
    4- checked vias to DDR3BRESET and DDR3ARESET they are showing 0 Volts. That indicates that SoC is not de asserting these resets.
    5-checked vias to DDRCLKOUT (A12, B12). That indicates that SoC is not generating these clocks.
    6- We have assembled 10 boards. We tested on 4 different boards we are having exact same issues.

    Now these finding are creating some questions in our mind. It would be immensely helpful if you could answer them.

    i- Are assumptions made in 4 and 5 are correct? If that so what can force SoC to do so?
    ii- We see that initialization gel script provided by TI indicates that "DDR initialization complete. DDR done" on our custom board. What does that mean. Does it mean training is done?
    iii- DDR3BRESET and DDR3ARESET are dependent on which clock sysclk or ddr3aclk/ddr3bclk (inputs to SoC).
    iv- In DSP no boot mode SoC is not executing anything on power up. SoC will only execute code provided through emulator via CCS. Is taht assumption is correct? or it executes some instructions from ROM/flash internal (on SoC) or external (board).

    BR
  • 0 in reply to suresh subramanium
    Prodigy 220 points
    I am still waiting for valuable suggestions from TI guys.
  • 0 in reply to suresh subramanium
    TI__Mastermind 46460 points

    Suresh,

     

    1- All power supplies are good except VCC2V5. VCC2v5 reports ~1.16 V all the time

    2- performed schematic symbol check. it reports no issue there.

    3- Checked Vias to VCC1V5 . All supplies are good.

    4- checked vias to DDR3BRESET and DDR3ARESET they are showing 0 Volts. That indicates that SoC is not de asserting these resets.

    5-checked vias to DDRCLKOUT (A12, B12). That indicates that SoC is not generating these clocks.

    6- We have assembled 10 boards. We tested on 4 different boards we are having exact same issues.

     

    i- Are assumptions made in 4 and 5 are correct? If that so what can force SoC to do so?

     

    THJ: Yes I believe they are correct.  I do not know what is causing it.  The problem appears to be fundamental.

     

    ii- We see that initialization gel script provided by TI indicates that "DDR initialization complete. DDR done" on our custom board. What does that mean. Does it mean training is done?

     

    THJ: It means that the logic believes all initialization and leveling is complete.  However, since the logic does not appear to be driving any outputs, I do not believe any initialization has been completed.

     

    iii- DDR3BRESET and DDR3ARESET are dependent on which clock sysclk or ddr3aclk/ddr3bclk (inputs to SoC).

     

    THJ: Each is operating on the DDR PLL for it’s logic block.  There are separate reference clock inputs and PLLs for each DDR interface.  Note that a DDR reference clock needs to be provided to both inputs even if only using one interface.

     

    iv- In DSP no boot mode SoC is not executing anything on power up. SoC will only execute code provided through emulator via CCS. Is taht assumption is correct? or it executes some instructions from ROM/flash internal (on SoC) or external (board).

     

    THJ: This is not completely true.  NOBOOT still runs some BOOTROM code but nothing is initialized.  It sits in a loop waiting for CCS to connect.  Note that CCS can be configured to auto-run a GEL at connect.  You can edit the CCXML file to prevent this.

     

    There are open suggestions from the previous post:

     

    To verify your initialization software, I recommend that you run the code for your custom board directly on the EVM. If you see a problem, then the software needs to be debugged.  If it works, even partially, on the EVM then we know there is a physical problem with your board.

     

    Please provide a report showing that the length matching rules have been met. The layout tool should be able to generate this.

     

    As said previously, your DDR3 interface appears to be completely non-functional. There must be some fundamental cause.  You will need to double-check the design in great detail to find the difference.

    Have you reviewed the KeyStone II Hardware Design Guide and the KeyStone DDR3 Layout Guide and the KeyStone II DDR3 Initialization Guide? There is also a checklist wiki page at: http://processors.wiki.ti.com/index.php/Keystone_Multicore_Device_Family_Schematic_Checklist.  You can also contact your FAE for assistance with your design.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points

    thanks for your response. I have attached length matching report that you asked for DDR3. The DDR3 paths are highlighted with yellow KEY_STONE_10.xlsxcolor. Again waiting for valuable input.

  • 0 in reply to suresh subramanium
    TI__Mastermind 46460 points

    Suresh,

    Yes, you sent a length report from the CAD software.  You need to show that the length matching rules have been met.  A report like the attached is needed.

    Tom

    6740.EVM_DDR3_Rules.xls

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points
    Thanks ,
    I will be back with those reports.

    Regards
  • 0 in reply to suresh subramanium
    Prodigy 220 points
    Hi Tom,
    Here is update from physical debug. We removed SoC from one board and tested the connections on Grid where SoC used to be connected.
    1- all connections of DVDD15 are intact and connected to VCC1V5.
    2- all connections of DVDD18 are intact and connected to VCC1V8.
    3- connections of DDR3BReset and DDR3AReset are intact and are connected to R470 and R648 respectively.
    4- connections of DDR3B_ECKP/N and DDR3A_ECKP/N are intact .

    Based upon these findings we have these questions. Please comment on them.
    i- What should be the status of DDRCLKOUT, DDR3BReset and DDR3AReset on power-up? (before any initialization through gel script).
    ii- if power and clock of DDR IO are good then what can prevent from generating DDR output clock and resets.
    iii- IDONE Indicates if set that the DDR system initialization has completed. This bit is set after all the
    selected initialization routines in PIR register have completed. If we see that part of code executes fine which means IDONE is set. This means all setup is done and at least DDRCLKOUT is generated from SoC. Is that assumption is right?
    iv- What else should we look in our physical testing.
  • 0 in reply to suresh subramanium
    TI__Mastermind 46460 points

    Suresh,

    I have indicated documentation and checklists for you to use.  I cannot debug your board for you.  The EVM is a working model that you can use for comparison.  The 66AK2H12 and associated software are known to function.

    IDONE is an incremental indicator of completeness.  It toggles after each stage of the initialization.  However, if there are no output signals, the status of the internal logic as reflected by IDONE is meaningless.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points
    Thank you for your insight, support and help on the on-going issue.

    Our assumption from IDONE signal is that atleast upto DDR PHY's DDR's input clock is reaching to DDR PHY and reset is also getting up to that level (DDR PHY) and some issue preventing the clock, reset and other signals to go out of the DDR IO's. But it seems from your email that this assumption is not correct ( DDR input clock and reset is reaching until DDR PHY) and we cannot conclude that DDR clock and reset is reaching upto DDR PHY. Please confirm.

    BR
    Suresh
  • 0 in reply to suresh subramanium
    TI__Mastermind 46460 points

    Suresh,

    I do not believe you can draw that conclusion from the IDONE status since you do not see any other indication that the PHY is operational.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points
    thanks Tom,
    We just checked all the things. The issue we were facing was due to mismatch in values of RR1. unluckily it was 240k instead of 240 ohms. We resolved our issue and now its running and all signals are fine. Thanks for all your assitance and support.
  • 0 in reply to suresh subramanium
    TI__Mastermind 46460 points

    Suresh,

    Thanks for the update.  We are glad that you found the issue and now have a functional board.  Your issue was unique.  We need to remember this for future reference.

    Tom