Part Number: 66AK2H12
Section 4.3.1.6 of SPRABI1B "DDR3 Design Requirements for KeyStone Devices Application Report" gives the following routing rule for data lanes:
"All nets within a single data group must be length-matched with +/- 10 mils."
If I assume, say 160 ps/inch of delay, that means all nets within a single data group must match to within 1.6 ps. That's comparable to the skew in the propagation time over the bond wires between the die and package pins. Some vendors will supply that info (e.g. Xilinx), but I haven't found it on TI's website. Can anyone point me to it?
Thanks.
