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66AK2H12: routing DDR3 traces

Charles Coldwell
Intellectual 420 points
Part Number: 66AK2H12

Section 4.3.1.6 of SPRABI1B "DDR3 Design Requirements for KeyStone Devices Application Report" gives the following routing rule for data lanes:

"All nets within a single data group must be length-matched with +/- 10 mils."

If I assume, say 160 ps/inch of delay, that means all nets within a single data group must match to within 1.6 ps.  That's comparable to the skew in the propagation time over the bond wires between the die and package pins.  Some vendors will supply that info (e.g. Xilinx), but I haven't found it on TI's website.  Can anyone point me to it?

Thanks.

  • 0
    TI__Guru**** 161600 points
    Hi Charles,

    The publicly available documents are DDR3 Design Requirements for KeyStone Devices, K2H Data Manual & the EVM reference files (www2.advantech.com/.../EVMK2HX.aspx). I have access to those docs and they don't provide this info.

    I've notified the K2H designers to elaborate further. Their feedback will be posed here.

    Best Regards,
    Yordan
  • 0
    TI__Mastermind 42545 points
    Hi Charles,
    We don't provide the length information between the die and package pins. That delay is built into the routing requirements provided. If you route your board to the +/-10mil guideline, that will compensate for the delays inside the part.
    Regards,
    Bill