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AM4378: AM4378 DDR3 trace routing

Jan Switzky
Prodigy 125 points

Part Number: AM4378

Hello,

I have designed a custom board with a AM4378, and it has 2 (16 bit) DDR3 chips on the same side of the board.  The size and shape of the board have forced me to locate the DDR3s in a way that doesn't quite match the recommendations in the datasheet (Figure 5-76), so I am having a difficult time determining Manhattan distance and max. trace lengths for address and clock nets.  Below is some information about the layout.

SEngineerin19042514200.pdf

FYI, we did build a first round of prototype boards, and the DDR3s do seem to be working fine, but I want to make sure we aren't just getting lucky, and would potentially have memory failures when we go to high volume production. Thanks in advance for your help.

Jan

  • 0
    TI__Guru*** 125430 points

    Fundamentally, I think you may have an issue in the placement of U3 and U4.  They look like they're placed as if you're going to do a balanced-T topology, but your actual routing is using a fly-by topology.  I believe that's why your trace lengths are so long.

    Best regards,
    Brad

    EDIT 4/26: Removed some of my original comments and markup... 

  • 0 in reply to Brad Griffis
    TI__Guru*** 125430 points
    FYI, I asked one of my colleagues who is deeper on the hardware side to review my comments and to make any further suggestions.
  • 0 in reply to Brad Griffis
    TI__Guru* 96081 points
    Actually, the Manhattan distance is just the x/y distance from point to point (not following the trace around). So you may be in violation of parameter 15 in table 5-58, plus you are close to the max trace lengths. Other factors which may affect robustness:
    -number of vias: Based on your drawing, it looks like you routed these signals on one layer, which is good. Any via mismatches will degrade the signal
    -Your drawing shows 90deg angles on the signals, which would not be good. I'm assuming this is just a simplified drawing and you have more gradual turns in those signals
    -stackup will also be important (Table 5-52). Hopefully you have a full ground reference under the DDR routing region

    As Brad said, I think ideally the placement and orientation of the memories relative to the processor could have been more optimized, and would have resulted in shorter traces and better routing.

    With your prototypes, some things that you can do to give you more confidence is to increase DDR frequency beyond 400MHz. Although this is out of spec, it can give you some idea of how much margin you have (ensure you adjust DDR configuration accordingly). Also, memory stress tests can be performed (Linux memtester is a good one, or set up some DMAs).

    Regards,
    James
  • 0 in reply to JJD
    TI__Guru*** 125430 points

    Jan,

    Sorry, I had my original drawing wrong.  (James, thanks for jumping in!)

    Here's a revised drawing.  The manhattan distance is just a simple x-y distance:

    According to your drawing this make the Manhattan distance for A13 equal to 976 mils + 244 mils = 1220 mils.

    However, the data sheet is looking for the LONGEST Manhattan distance.  So I believe that's going to correspond to A8:

    Spec 15 in Table 58 (CK and ADDR_CTRL Routing Specification) of the data sheet is saying that all your trace lengths should be +/-50 mils of this longest Manhattan distance.

    I hope this helps clarify things, and sorry for any confusion generated by my original post. 

    Best regards,

    Brad

  • 0 in reply to Brad Griffis
    Prodigy 125 points

    Brad,

    Thanks for checking into this for me.  I'll plan to make the necessary changes on the next spin.

    Regards,

    Jan