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C6657 DDR3 initialization

g.f.
Guru 15510 points

Hi,

I have a question about C6657 DDR3.

I'm using Processor SDK of C6657 at custom board and have question about DDR3 initialization process.
This initialization is written in "platform.c" and "evmc6657.c".

In "platform.c", there are DDR3 memory test process after DDR3 initialization and Hardware leveling.
If DDR3 memory test failed, it will re-initialize PLL and DDR3(also Hardware leveling) again until it pass the test or loop 10 times.
Do I need this process(re-initialization) on custom board and why the maximum loop count is 10?

On custom board, DDR3 memory test failed and it never pass the test.
But when I increment the loop count from 10 to 100, it pass the test when the loop count was 50.
And it seem that C6657 can access DDR3 successfully after memory test.

best regards,
g.f.

  • 0
    TI__Mastermind 46460 points

    g.f.,

    No, the repeat loop in the configuration of the DDR3 Controller and PHY (and PLLs) is not required in your product.  This was added to the code that supported the KeyStone-I EVMs back when we had occasional instability (2012). At that time, a very small percentage (<2%) of C6678 and C6670 EVMs would occasionally fail DDR3 initialization.  It was found at that time that a repeated initialization would solve the problem.  The root cause of the problem was the set of PHY_INIT values calculated based on the board layout.  Version 10 of the PHY_CALC worksheet contained corrected equations to resolve this issue.  (The latest release is v11.)

    The PHY_CAL and REG_CALC worksheets are complement tools along with the KeyStone I DDR3 Initialization Application Report (SPRABL2).  These worksheets must be used to commission your software to run on your custom board.  The PHY and Controller values contained in the sample software are only correct for the EVMs.

    You should not require looping at all.  A single configuration will be sufficient.  We suggest that you validate that you length matching rules and other design guidelines from DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1).  (There are many E2E posts discussing this.)  Then the clock and data strobe lengths get used in the PHY_CALC worksheet to calculate the leveling initialization values.  The SDRAM datasheet must be used to compute the Controller register values using the REG_CAL worksheet and/or the DDR3 Memory Controller User Guide (SPRUGV8).

    We recommend that you then validate your board using the GEL script provided.  This is a much simpler environment for board validation.  Then after you have the DDR3 operating correctly using the GEL script with CCS, you can integrate the values into your application code.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Guru* 81335 points
    Tom,
    Thank you for the clarification. I have deleted my previous post.
  • 0 in reply to Tom Johnson 16214
    Guru 15510 points
    Hi Tom,

    Thank you for the answer.
    I understood that repeat loop are not required.

    By the way, the DDR3 initialization process in C6657 PDK, the values of DATAn_PHY_WRLVL_INIT_RATIO and
    DATAn_PHY_GATELVL_INIT_RATIO are setup to the wrong registers.
    DATAn_PHY_WRLVL_INIT_RATIO are setup to DDR3_CONFIG_6 - DDR3_CONFIG_9,
    DATAn_PHY_GATELVL_INIT_RATIO are setup to DDR3_CONFIG_18 - DDR3_CONFIG_21 which register are NA for C665x.
    Please check the "evmc6657.c" in pdk_c665x_2_0_0/packages/ti/platform_lib/src.

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Mastermind 46460 points

    g.f.

    There was confusion at one time.  I believe that the C6657 GEL file, the PHY_CALC v11 worksheet, the DDR3 Initialization Appnote and the DDR3 UG are all correct in this regard.  The correction to the PDK code may still be pending.

    Tom