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AM572x IVA questions

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: AM5728

Hi,


I have some question for IVA system of AM5728. Please see the below.


1) According to the TRM chapter 6 IVA subsystem,  it is written as the below.


    The IVA-HD subsystem is a set of video encoder and decoder hardware accelerators. The

    list of supported codecs can be found in the software development kit (SDK) documentation.

 Can I get this SDK? Is it Linux SDK?


2) bit of CM_CLKMODE_DPLL_IVA register : 10bit[DPLL_LPMODE_EN] - Low Power mode of the DPLL is disabled
  Is this Low power mode same as Low power stop in Table 3-45 DPLL Power Modes?

3)  bit of CM_CLKMODE_DPLL_IVA register :2:0 bit[DPLL_EN] - Put the DPLL in Idle Bypass Low Power mode
  Is this "Put the DPLL in Idle Bypass Low Power mode" same as Low power bypass in Table 3-45?
 
4) If DPLL_EN(2:0) bits are 0x5, IVA_GCLK is stopped becuase CLKOUT_M2(Figure 3-59 DPLL_IVA Overview) is stopped. Is my understanding right?

 Please advise me.

I appreciate your quick reply.

Best regards,

Michi

 

  • 0
    TI__Guru**** 393215 points
    Hi,

    1. Yes, you can find it here: software-dl.ti.com/.../index_FDS.html
    2. No, this is not the same. See section 3.6.3.8.3 of the TRM.
    3. Yes.
    4. No, in this case the DPLL is bypassed and IVA_GCLK =IVA_DPLL_HS_CLK.
  • 0 in reply to Biser Gatchev-XID
    Guru 10030 points
    Dear Biser-san,

    Thank you for your quick reply.

    I would like to confirm No2.question.

    According to Tabl3e 3-65 DPLL_MPU Modes, "Low-Power Stop" is not supported( it is not available). So [10] bit [DPLL_LPMODE_EN] of CM_CLKMODE_DPLL_IVA register is not the same as Table 3-45 DPLL Power Modes. If it is so, DPLL_LPMODE[10] bit is the same as "Low-Power Bypass"?

    Please advise me again.

    Best regards,
    Michi
  • 0 in reply to Michi Yama
    TI__Guru**** 393215 points
    DPLL_LPMODE[10] controls only the power mode of the DPLL. See section 3.6.3.3.3. Low-power mode can be enabled either when DPLL is bypassed or when the input and output clock frequencies are low.