We are struggling to get reasonable NAND performance via the OMAP L138 or L132 EMIFA subsystem. Similar behaviour has been seen on both the TI LCDK board and our own in-house L132-based board. Tracing the signals to the NAND chip via DSO shows signalling which does not match what would be expected for the clock being fed into the EMIFA.
Our board has a 24MHz crystal for CLKIN. PLLM is set to max (i.e. 31 + 1 = x32) with POSTDIV of 3 + 1 =4. All PLLDIV values are default. I have (using OCSEL settings to send different clock signals to the CLKOUT pin) confirmed that various of the PLL0_SYSCLK frequencies match what I expect given the multiplier/divider settings. From that I am confident that the DIV4.5 value is as expected, giving an EMA_CLK of ~170MHz. I am aware that this goes above the maximum of 150MHz for async, but I had it at that setting for the current set of DSO readings. It was at max given I saw a slight improvement in early tests from 150MHz and noting appeared to suffer in short testing. From this I would expect a clock period of ~6ns. Based on the timing in figure 20-10 and setup, strobe, and hold values in the async configuration register to match (2, 3, 2) I would expect EMA_OE to be down for ~24ns. Instead it is down for ~350ns, over an order of magnitude longer. The result is a read rate of < 2MB/s, despite the NAND chips being able to cope with a far higher rate.
Below is a dump of the relevant register settings used (with no NAND access underway):
CFGCHIP3 0xff26 - Relevant bits are bits 1-2 enabling DIV4.5 and setting EMA_CLKSRC to the DIV4.5 clock
PLL registers:
PLLCTL 0x49
PLLM 0x1f
PREDIV 0x8000
PLLDIV1 0x8000
PLLDIV2 0x8001
PLLDIV3 0x8002
PLLDIV4 0x8003
PLLDIV5 0x8002
PLLDIV6 0x8000
PLLDIV7 0x8005
OSCDIV 0x8000
POSTDIV 0x8003
PLLCMD 0x1
PLLSTAT 0x6
ALNCTL 0x1ff
DCHANGE 0x0
CKEN 0x3
SYSTAT 0x1fe
EMIFA registers
AWCC 0xf0000080 (and 0x80)
CE3CFG 0xc466234
NANDFCR 0x12 - CS3 enabled, with 4-bit ECC
NANDFSR 0x3 - both EMA_WAIT pins high
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