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Add a custom memory region in Keystone II devices

Hi all,

The default memory regions are defined in the auto generated linker.cmd file and is as follows:

MEMORY
{
L2SRAM (RWX) : org = 0x800000, len = 0x100000
MSMCSRAM (RWX) : org = 0xc000000, len = 0x200000
DDR3 : org = 0x80000000, len = 0x80000000
}

This is done during system start up and initialization and is handled by XDCtools.

We can define sections in the above memory regions in the custom xdt file that will add these sections in addition to the default sections created by the XDCtools.

For example:

.gdataddr: load >> DDR3
.gdatamsmc: load >> MSMCSRAM
.gdatal2sram: load >> L2SRAM

How can we define custom memory regions, bypassing the default memory regions created by the XDCtools?

We would like to do something like this, for example:

MEMORY
{
L2SRAM (RWX) : org = 0x800000, len = 0x100000
MSMCSRAM (RWX) : org = 0xc000000, len = 0x200000
DDR3 : org = 0x80000000, len = 0x40000000

GDATA : org = 0xC0000000, len = 0x40000000

}

And create sections in our custom memory region:

.gdataddr: load >> GDATA 

Thanks

  • I've moved your thread to the device forum. I believe the Processors SDK has a specific way to do this.

    Todd
  • I think, you can add one more linker command file to that project for "GDATA" entry but that should not create any conflict with default.
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  • Hi Titus,

    Thanks for the reply.

    As mentioned in the query I need to do something like this:

    MEMORY
    {
    ...
    ...
    DDR3 : org = 0x80000000, len = 0x40000000
    GDATA : org = 0xC0000000, len = 0x40000000
    }

    I need to reduce the length of DDR3 section and make a new memory section "GDATA" in the left over memory. Since default assigns
    DDDR3 : org = 0x80000000, len = 0x80000000, hence there will be an overlap of memory regions if I use the default assignments + my custom linker command file with GDATA : org = 0xC0000000, len = 0x40000000. So I need to override the default memory sections.

    Regards, Yunas
  • I feel like I have done exactly what you are asking, so I'll give this a shot.

    Two parts.

    Part 1 is to define the memory regions.
    Open a CCS Debug View in CCS. Click on Tools->RTSC Tools->Platform->Edit/View.
    My packages are in C:\ti\bios_6_45_01_29\packages. My Package Name is ti.platforms.evmAM5728. Your might be different, so select yours as needed. Click Next.
    In the External Memory block you can edit or add new sections as needed. I've added several sections and change the location and size of existing sections.

    Part 2 is to use the new sections.
    In your .cfg file you should have a sectMap section. Here is an example of mine showing the new sections I have allocated and used.

    /* Allocate sections to memory */
    Program.sectMap[".resource_table"] = "EXT_RAM";
    Program.sectMap[".vecs"] = "EXT_RAM";
    Program.sectMap[".cinit"] = "EXT_RAM";
    Program.sectMap[".init_array"] = "EXT_RAM";
    Program.sectMap[".cio"] = "EXT_RAM";
    Program.sectMap[".rodata"] = "EXT_RAM";
    Program.sectMap[".neardata"] = "EXT_RAM";
    Program.sectMap[".far"] = "EXT_RAM";
    Program.sectMap[".bss"] = "EXT_RAM";
    Program.sectMap[".const"] = "EXT_RAM";
    Program.sectMap[".text"] = "EXT_RAM";
    Program.sectMap[".switch"] = "EXT_RAM";
    Program.sectMap[".stack"] = "EXT_RAM";
    Program.sectMap[".fardata"] = "EXT_RAM";
    Program.sectMap[".far:taskStackSection"] = "EXT_RAM";
    Program.sectMap["systemHeap"] = "EXT_RAM";
    Program.sectMap["myHeapSection"] = "EXT_RAM";
    Program.sectMap[".UnitTestData"] = "EXT_RAM";
    Program.sectMap[".calibration_Data"] = "CAL_RAM";
    Program.sectMap[".fpga_Download"] = "FPGA_RAM";
    Program.sectMap[".hpi_Log_Data"] = "HPI_RAM";
    Program.sectMap["BOARD_IO_DELAY_DATA"] = "OCMC_RAM1";
    Program.sectMap["BOARD_IO_DELAY_CODE"] = "OCMC_RAM1";
    Program.sectMap[".tracebuf"] = "TRACE_BUF";
    Program.sectMap[".noncached_Program_Data"] = "L2SRAM";
  • In addition to what Christopher wrote

    This issue was discussed a lot in the forum.  Some postings are listed below:

    https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/527763

    https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/198130

    https://e2e.ti.com/support/embedded/tirtos/f/355/t/110524

    https://e2e.ti.com/support/embedded/tirtos/f/355/t/84659

    Please read the above, and if you are happy with the information close the thread

    Ran

  • Thanks Ran, Christopher. This is exactly what I was looking for.

    Regards