DM385 + IPNC RDK3.5 + kernel 2.6.37 -> nand flash driver support needed?

Hi Pavel Botev ,

respective file observations:

1-> board/ti/dm385_ipnc/evm.c

int board_init()
{
gpmc_init(); //arch/arm/cpu/arm_cortexa8/ti81xx/mem.c

#ifndef CONFIG_NOR
gpmc_set_cs_buswidth(0, get_sysboot_ipnc_bw()); //from ipnc_bw it is checking control_status and then set buswidth
#endif
}

2-> cpu/arm_cortexa8/ti81xx/sys_info.c

now in these file it is checking at control_status pin to determine whether it will be x8 / x16.

get_sysboot_ipnc_bw()
{
bw = __raw_readl(CONTROL_STATUS) & (SYSBOOT_IPNC_BW_MASK);
bw >>= SYSBOOT_IPNC_BW_POS;
if (bw == 0) /* 16-bit nand if BTMODE BW pin on board is ON */
return 1;
else if (bw == 1)/* 8-bit nand if BTMODE BW pin on board is OFF */
return 0;
}

3-> based on get_sysboot_ipnc_bw, in below function we set buswidth.

arch/arm/cpu/arm_cortexa8/ti81xx/mem.c

void gpmc_set_cs_buswidth(u32 cs, u32 bw){
gpmc_cfg = (struct gpmc *)GPMC_BASE;
cfg = (struct gpmc_cs *)(&gpmc_cfg->cs[cs]);

config1 = readl(&cfg->config1);

/* clear and set device size bits (13:12) */
config1 &= (~0x00003000);
config1 |= (bw << 12);
writel(config1, &cfg->config1);
}

that's it now can you tell me where am i missing.

yes changing, changing control status value was my mistake but i was making sure.

thanks & regards,
Ganesh

Ganesh Biradar said:

that's it now can you tell me where am i missing.

You are missing the point that CONTROL_STATUS[16] BW bit value depends on hardware (the value depends on the state of the BOOTM[12] pin), [16] BW bit value should not be set by software. Software only check what is the value there.

Regards,
Pavel

Hi Pavel Botev,

 i Understood what you said i have already removed the value which i set, now can you tell me, if it is detecting properly BTMODE[12] as 0[x8], then setting bw to x8 then why it is not able to detect NAND Flash or in any other place i have to make any changes.

regards,

Ganesh

If it detect properly BTMODE[12] as 0 (8-bit) and then set GPMC_CONFIG1_0[13:12] DEVICESIZE to 0 (8-bit), then you should fix the maf_id/dev_id issue.

Regards,
Pavel

Hi Pavel Botev (1176686) ,

following is the log i got from u-boot stage after i made changes to gpmc_config register:

NAND:  HW ECC BCH8 Selected

DM385 : GPMC -> 810 CONTROL_STATUS -> 317

DM385 -> 1 : busw: 0

DM385 -> nand_get_flash_type: ID read 17,17

DM385 -> nand_get_flash_type: ID 17,17 against 17,17

0 MiB

i made change to support x8 in below file:

arch/arm/cpu/arm_cortexa8/ti81xx/mem.c

void gpmc_set_cs_buswidth(u32 cs, u32 bw)

{

.....

config1 |= (bw << 12);

//writel(config1, &cfg->config1);

writel(0x00000810, &cfg->config1);

}

but nothing changed.

thanks & regards,

Ganesh

Ganesh,

When I explained that you should fix the BOOTM[12] pin value, not to hack the u-boot code base, you state that you understand. But you are doing it over and over again.

Without any SW modifications in u-boot, what is the value you have in CONTRL_STATUS[16] BW bit?

Hi Pavel,

without any software change just added debug log,

NAND: HW ECC BCH8 Selected
DM385 : GPMC -> 1800 CONTROL_STATUS -> 317
DM385 -> 1 : busw: 2
DM385 -> nand_get_flash_type: ID read 17,17
DM385 -> nand_get_flash_type: ID 17,17 against 17,17
0 MiB

these what i got.

anything else!

regards,
Ganesh

Ganesh Biradar said:

CONTROL_STATUS -> 317

So you have CONTROL_STATUS[16] BW = 0, right?

And what you have by default (without SW modifications) in the below function, return 1 or return 0?

/************************************************************
 * get_sysboot_ipnc_bw(void) - return buswidth from CONTROL_STATUS
 ************************************************************/
u32 get_sysboot_ipnc_bw(void)
{
    int bw;
    bw = __raw_readl(CONTROL_STATUS) & (SYSBOOT_IPNC_BW_MASK);
    bw >>= SYSBOOT_IPNC_BW_POS;
    if (bw == 0)    /* 16-bit nand if BTMODE BW pin on board is ON */
        return 1;
    else if (bw == 1)/* 8-bit nand if BTMODE BW pin on board is OFF */
        return 0;
    /* error case */
    return 0; /* it never return from here */
}

Hi Pavel,

these what i have

u32 get_sysboot_ipnc_bw(void)
{
int bw;
bw = __raw_readl(CONTROL_STATUS) & (SYSBOOT_IPNC_BW_MASK);
bw >>= SYSBOOT_IPNC_BW_POS;
if (bw == 0) /* 16-bit nand if BTMODE BW pin on board is ON */
return 1;
else if (bw == 1)/* 8-bit nand if BTMODE BW pin on board is OFF */
return 0;
/* error case */
return 0; /* it never return from here */
}

one more thing, when we read maf_id & dev_id nothing but READ_ID -> we read particular address where all information related to NAND will be available right, where mapping of these register will be available. so that i can check that too.

thanks & regards,
Ganesh

I mean what is the return value from get_sysboot_ipnc_bw(), 1 or 0?

Hi Pavel,

how am i suppose to get the value, when i add some print statement uboot won't boot, what ever the value i get i have to print in nand driver.

one more thing, when we read maf_id & dev_id nothing but READ_ID -> we read particular address where all information related to NAND will be available right, where mapping of these register will be available. so that i can check that too.

regards,
Ganesh

Ganesh Biradar said:

how am i suppose to get the value, when i add some print statement uboot won't boot, what ever the value i get i have to print in nand driver.

Can you try the below approach, will it print successful?

u-boot/board/ti/dm385_ipnc/evm.c

int board_init(void)
{
    u32 regVal;
   +u32 temp;

.....

    +temp = get_sysboot_ipnc_bw();
    +printf("get_sysboot_ipnc_bw = %d\n",temp);
    gpmc_set_cs_buswidth(0, get_sysboot_ipnc_bw());

}

Hi Pavel Botev ,

well i tried earlier also, board didn't boot up. even after you asked i added print statement board is not booting.

regards,
Ganesh

Can you try to print that value in:

u-boot/arch/arm/cpu/arm_cortexa8/ti81xx/mem.c

void gpmc_set_cs_buswidth(u32 cs, u32 bw)
{
u32 config1;
struct gpmc_cs *cfg;

printf("bw = %d/n",bw)
....
}

Hi Pavel,

well i tried that too also earlier as it was not booting so i'm reading those value in nand driver.
i tried again still it is not booting up. if i remove the print statement it is booting.

regards,
Ganesh

Ganesh Biradar said:

i'm reading those value in nand driver

Do you mean NAND driver in Linux kernel?

Can you stop the boot process, enter into the u-boot prompt and check what you have in CONTROL_STATUS and GPMC_CONFIG1_0 registers? Use the default u-boot code base.

Regards,
Pavel

Hi Pavel Botev,

"Do you mean NAND driver in Linux kernel?"

No I'm telling you about nand driver in uboot,

uboot/drivers/mtd/nand/nand_base.c

please do check that too, working of nand driver in linux kernel works same as in uboot also.

>>>>>>>>>>>>>>>>>>> boot log from uboot <<<<<<<<<<<<<<<<<<<<

NAND: Searching for NAND device @ GPMC CS:0
DM385 -> drivers/mtd/nand/ti18xx_nand.c -> board_nand_init() -> gpmc_cfg->cs[cs].config1 -> 0x1000 -> x16 bit
HW ECC BCH8 Selected
DM385 : GPMC -> 1800 CONTROL_STATUS -> 317
DM385 -> 1 : busw: 2
DM385 -> nand_get_flash_type: ID read 17,17
DM385 -> nand_get_flash_type: ID 17,17 against 17,17
0 MiB

--------->

arch/arm/cpu/arm_cortexa8/ti81xx/mem.c

static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
        M_NAND_GPMC_CONFIG1,
        M_NAND_GPMC_CONFIG2,
        M_NAND_GPMC_CONFIG3,
        M_NAND_GPMC_CONFIG4,
        M_NAND_GPMC_CONFIG5,
        M_NAND_GPMC_CONFIG6, 0
};

in include/asm/arch-ti81xx/mem.h +100

#ifdef CONFIG_DM385
#define M_NAND_GPMC_CONFIG1     0x00001800      //0x00001810
#define M_NAND_GPMC_CONFIG2     0x00060600      //0x001e1e00
#define M_NAND_GPMC_CONFIG3     0x00060601      //0x001e1e00
#define M_NAND_GPMC_CONFIG4     0x04010401      //0x16051807
#define M_NAND_GPMC_CONFIG5     0x00040506      //0x00151e1e
#define M_NAND_GPMC_CONFIG6     0x04000580      //0x16000f80
#define M_NAND_GPMC_CONFIG7     0x00000008
#else 
...........

can we change these value for CONFIG1 to use x8 bit

regards,
Ganesh

Ganesh Biradar said:

No I'm telling you about nand driver in uboot,

uboot/drivers/mtd/nand/nand_base.c

How exactly you print the CONTROL_STATUS and GPMC_CONFIG1_0 registers values there?

Ganesh Biradar said:

please do check that too

What should I check here?

Hi Pavel Botev ,

in./drivers/mtd/nand/nand_base.c file

int nand_scan_ident(struct mtd_info *mtd, int maxchips)
{
..........
printk(KERN_INFO"DM385 : GPMC -> %x CONTROL_STATUS -> %x\n",__raw_readl(0x50000060),__raw_readl(0x48140040));
.........
}

log: DM385 : GPMC -> 1800 CONTROL_STATUS -> 317

regards,
Ganesh

Ganesh Biradar said:

printk(KERN_INFO

I think printk() can be used only in linux kernel. In u-boot, printf() should be used.

Can you stop the boot process, enter into the u-boot prompt and check what you have in CONTROL_STATUS and GPMC_CONFIG1_0 registers? Use the default u-boot code base.

Hi Pavel,

default uboot used, in uboot stage

DM385_IPNC#md 0x50000060 1
50000060: 00001800 ....
DM385_IPNC#md 0x48140040 1
48140040: 00000317 ....

thanks & regards,
Ganesh

Ganesh,

Please apply the below changes in the u-boot code base, try with this new u-boot and provide me the values you have in the u-boot prompt.

u-boot/arch/arm/include/asm/arch-ti81xx/cpu.h

-#define SYSBOOT_IPNC_BW_POS (12)
+#define SYSBOOT_IPNC_BW_POS (16)

u-boot/arch/arm/cpu/arm_cortexa8/ti81xx/sys_info.c

u32 get_sysboot_ipnc_bw(void)

-if (bw == 0) /* 16-bit nand if BTMODE BW pin on board is ON */
-return 1;
-else if (bw == 1)/* 8-bit nand if BTMODE BW pin on board is OFF */
-return 0;

+if (bw == 0) /* 8-bit nand if BTMODE BW pin on board is OFF */
+return 0;
+else if (bw == 1)/* 16-bit nand if BTMODE BW pin on board is ON */
+return 1;

Hi Pavel,

 with respect changes you asked for with clean unmodified except above changes used, following is debug log,

U-Boot 2010.06-dirty (Aug 17 2016 - 09:14:21) DM385_IPNC_3.50.00

DM385-GP rev 1.1

ARM clk: 720MHz
DDR clk: 533MHz
L3 clk: 200MHz
IVA clk: 450MHz
ISS clk: 400MHz
DSP Default OFF
DSS Default OFF

I2C:   ready
DRAM:  1 GiB
NAND:  HW ECC BCH8 Selected
0 MiB
MMC:   : 0, ON-BOARD SDIO: 1
Net:   cpsw
Hit any key to stop autoboot:  0
DM385_IPNC#md 0x50000060 1
50000060: 00000800    ....
DM385_IPNC#md 0x48140040
48140040: 00000317    ....

well still i have not got any NAND device yet.

few clarification needed:

Question 1:

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

DM385 Custom board:

[DM385] GPMC_CS0 pin-------------Directly connected to<NOTE>----------------------------------ChipEnable pin [NAND FLASH]

NOTE: for connection their is a provision for external pull up of 3.3v is available but not used.

In DM385 CBB board schematic, NAND Flash CE pin is connected to GPMC_CS0 as well as external pull up in between.

Is external pull on CS0 pin is needed or not?

Question 2:

-------------------------------------------------------------------------------------------------------------------------------------------

When i boot from NAND flash as i remove BTMODE[2] jumper, it's boot perfectly as it has prebuilt uboot image, while initially CS0 pin is high, but once it start it becomes low in NAND flash booting.

But where as in case of sd boot, when we try to access NAND flash, CS0 pin state is always high not changing at all.

So what could be the reason behind these scenario?

 

 

Ganesh Biradar said:

 with respect changes you asked for with clean unmodified except above changes used, following is debug log,

U-Boot 2010.06-dirty (Aug 17 2016 - 09:14:21) DM385_IPNC_3.50.00

DM385-GP rev 1.1

ARM clk: 720MHz
DDR clk: 533MHz
L3 clk: 200MHz
IVA clk: 450MHz
ISS clk: 400MHz
DSP Default OFF
DSS Default OFF

I2C:   ready
DRAM:  1 GiB
NAND:  HW ECC BCH8 Selected
0 MiB
MMC:   : 0, ON-BOARD SDIO: 1
Net:   cpsw
Hit any key to stop autoboot:  0
DM385_IPNC#md 0x50000060 1
50000060: 00000800    ....
DM385_IPNC#md 0x48140040
48140040: 00000317    ....

This looks correct regarding 8-bit NAND settings.

Ganesh Biradar said:

well still i have not got any NAND device yet.

few clarification needed:

I will have a look in these and come back to you when I have something.

Regards,
Pavel

Ganesh Biradar said:

Question 1:

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

DM385 Custom board:

[DM385] GPMC_CS0 pin-------------Directly connected to<NOTE>----------------------------------ChipEnable pin [NAND FLASH]

NOTE: for connection their is a provision for external pull up of 3.3v is available but not used.

In DM385 CBB board schematic, NAND Flash CE pin is connected to GPMC_CS0 as well as external pull up in between.

Is external pull on CS0 pin is needed or not?

On EVMs, there is switch. The output of this switch (when the switch is disabled) is floating, thus there must be external pull up.

On your custom board, you do not have a switch, and GPMC_CS0 has IPU (internal pull up). But this IPU might be weak for the specific external NAND chip, so I would recommend to have external pull up there, just in case.

Ganesh Biradar said:

Question 2:

-------------------------------------------------------------------------------------------------------------------------------------------

When i boot from NAND flash as i remove BTMODE[2] jumper, it's boot perfectly as it has prebuilt uboot image, while initially CS0 pin is high, but once it start it becomes low in NAND flash booting.

But where as in case of sd boot, when we try to access NAND flash, CS0 pin state is always high not changing at all.

So what could be the reason behind these scenario?

So, you are able to boot from NAND flash successful on your custom board? The NAND chip is properly detected there, and you have the correct values for maf_id/dev_id? And the issue appear when you switch from NAND boot to SD boot?

Regards,
Pavel

Hi Pavel Botev ,

"So, you are able to boot from NAND flash successful on your custom board? The NAND chip is properly detected there, and you have the correct values for maf_id/dev_id? And the issue appear when you switch from NAND boot to SD boot?"

>> Yes i'm able boot from NAND flash successfully. i'm able to boot from NAND but the image it carries is preloaded that came from client. we don't have confirmation whether image were flashed by client or not. but we can boot. i can't see maf_id & dev_id because most of logs are suppressed. just uboot name and its version. that's it.

>> the issue is i have to flash my images, for that first i have to first detect NAND in uboot as well as in kernel. priority NAND support in uboot.

>> If it is booting from NAND flash then also do i need to provide external pull up on GPMC_CS0 --- CE.

Regards,
Ganesh

Ganesh Biradar said:

Yes i'm able boot from NAND flash successfully. i'm able to boot from NAND but the image it carries is preloaded that came from client. we don't have confirmation whether image were flashed by client or not. but we can boot. i can't see maf_id & dev_id because most of logs are suppressed. just uboot name and its version. that's it.

Can you provide me full u-boot console log output when booting from NAND? I also need GPMC registers dump when booting from NAND and when booting from SD card. Take these GPMC registers value from the u-boot prompt with the md command.

Ganesh Biradar said:

If it is booting from NAND flash then also do i need to provide external pull up on GPMC_CS0 --- CE.

Yes, I still suggest to provide external pull up.

Regards,
Pavel

Hi Pavel Botev ,

From NAND Boot,

U-Boot 2010.06 (Apr 20 2015 - 11:03:29) DM385.10 600/1066/720/800



U-Boot 2010.06 (Apr 20 2015 - 11:03:54) DM385.10 600/1066/720/800

[c6xdsp ] Remote Debug Shared Memory @ 0xbff00000
[m3video] Remote Debug Shared Memory @ 0xbff05020
[m3vpss ] Remote Debug Shared Memory @ 0xbff0a040

/dev/mem opened.
DDR IOs RX is shutdown

>>> Well the problem here is their no shell prompt to access gpmc register, after above logs screen goes blank.

thanks & regards,
Ganesh

Ganesh,

This does not seem to me like valid u-boot loading. Can you provide me a screen shot (print screen) of what you see in the console when boot from NAND?

Regards,
Pavel

Hi Pavel Botev,

These are GPMC register previously you ask from sd card booting:

DM385_IPNC#md 0x50000060
50000060: 00000800 00060600 00060601 04010401    ................
50000070: 00040506 04000580 00000848 17171717    ........H.......
50000080: 17171717 17171717 00000000 00000000    ................
50000090: 00001000 00101001 22060514 10057016    ...........".p..
500000a0: 010f1111 8f070000 00000f00


DM385_IPNC#md 0x48140960
48140960: 00050001 00050001 00050001 00050001    ................
48140970: 00050001 00050001 00050001 00050001    ................
48140980: 00050001 00050001 00050001 00050001    ................
48140990: 00050001 00050001 00050001 00050001    ................
481409a0: 00040001 00040001 00040001 00040001    ................
481409b0: 00060001 00040001 00060001 00040001    ................
481409c0: 00060080 00060080 00060001 00060001    ................
481409d0: 00060001 00060080 00060001 00060001    ................
481409e0: 00060001 00060002 00060001 00060080    ................
481409f0: 00060001 00060080 00060001 00060001    ................
48140a00: 00060001 00060001 00040001 00040001    ................
48140a10: 00060002 00040001 000e0080 000e0001    ................
48140a20: 000c0001 000e0001 000e0001 000c0001    ................
48140a30: 000c0001 000c0001 000c0001 000c0001    ................
48140a40: 000c0001 000c0001 000c0001 000c0001    ................

And from NAND flash boot screen shot:

I will inform about external pull up on CS0 once hardware chnage is done.

thanks & regards,

Ganesh

Ganesh,

This NAND boot log has nothing common with successful NAND boot process. What makes you think you have successful NAND boot in your custom board?

Regards,
Pavel

Hi Pavel Botev ,

Just got information that client is booting from NAND not from SD card(I don't have log so i can't tell more information on that). So we can confirm that it is successfully booting from NAND. but coming to my case, i have to provide support in SD card boot to detect NAND flash.

Regards,
Ganesh

Ganesh Biradar said:

So we can confirm that it is successfully booting from NAND.

Based on the log and the screen shot you sent, I can not agree with that.

Hi Pavel Botev ,

I'm not talking about Screenshot log but rather the binary file which we sended to client those booting properly. Those log i don't have.

regards,
Ganesh

Ganesh Biradar said:

the binary file which we sended to client those booting properly.

What is this binary file? And on what board they boot successful from NAND this binary file?

Regards,
Pavel

Hi Pavel Botev ,

i was referring uboot,uImage & rootfs(complete) as binary.

Well got full information from client, third party to my client has provided some working binary to them for testing, with suppressed each and every log and steps i don't know how they did this. But client has flashed binary in NAND. the log which i have sended is from the binary image. My companies client doesn't have source code of the binary file. so no help on that part. can't get any information w.r.t register values.

>>>>>"What ever the uboot, uimage was sended from our side is still not yet being used" - sorry about the wrong information on that part.

Provided external pull up on CS0 to CE but no affect on outcome. still it is not able to detect NAND.

Now tell me what can i do?

Regards,
Ganesh

Ganesh,

Can you request from your client the console log from the u-boot binary? Do they flash and run this u-boot binary on the same custom board as you have on your side?

Meanwhile you should proceed with debugging why you can not get the correct maf_id/dev_id.

Regards,
Pavel

Hi Pavel,

"Can you request from your client the console log from the u-boot binary? Do they flash and run this u-boot binary on the same custom board as you have on your side?"

>>>>> same uboot log which i have posted as screenshot. yes they flashing to custom board only. first they are flashing and then they are providing the board to us.

"Meanwhile you should proceed with debugging why you can not get the correct maf_id/dev_id."

>>>>> I'm doing these things from past two weeks.

can you tell from where it will read maf_id & dev_id. i know that READ_ID will give the information but still need to know. it will try to read from some address.

regards,
Ganesh

regards,
Ganesh

Ganesh Biradar said:

"Can you request from your client the console log from the u-boot binary? Do they flash and run this u-boot binary on the same custom board as you have on your side?"

>>>>> same uboot log which i have posted as screenshot. yes they flashing to custom board only. first they are flashing and then they are providing the board to us.

Then I can state this is not successful NAND boot. Based on the screen shot, I can state that your board can not boot from NAND.

Regards,
Pavel

Ganesh Biradar said:

can you tell from where it will read maf_id & dev_id. i know that READ_ID will give the information but still need to know.

I am not sure I understand this. Can you provide more details of what exactly you need to know?

Hi Pavel Botev ,

"Then I can state this is not successful NAND boot. Based on the screen shot, I can state that your board can not boot from NAND."

>> i have set up TV with board, booted from NAND able to see some four block of images. based on that client and my senior confirmed it is working. beyond that i can't say anything.

"I am not sure I understand this. Can you provide more details of what exactly you need to know?"

You already knew i tried everything but still i'm not getting. sorry but you have to tell me where i can put some debug messages to get more info.

regards,
Ganesh

Ganesh,

No matter how debug messages you add to the u-boot code base, if your board HW is not correct, the NAND will not start to work.

I would suggest you to try the things described in the below e2e post:
e2e.ti.com/.../1948795

BR
Pavel

Hi Pavel Botev ,

The NAND support in uboot Task has taken up by my manager. if he found any solution/progress on that i will update.

thanks & regards,
Ganesh

Ganesh,

I see that your Spansion S34ML01G1 (device ID 0xF1, Man ID 0x01) is in the nand_ids.c So the main issue is that you are not getting the correct values for dev id and man id, but you have 0x17 for both.

Check board_nand_init(), make sure you are not getting into the case where nand->options is set with NAND_BUSWIDTH_16.

Check also nand_set_defaults, make sure busw is not 0x2. Make sure chip->read_byte = nand_read_byte.

See also the below links:

e2e.ti.com/.../358047
e2e.ti.com/.../974901

www.cypress.com/software-and-drivers-cypress-flash-memory

Regards,
Pavel

Hi Pavel Botev ,

"Check board_nand_init(), make sure you are not getting into the case where nand->options is set with NAND_BUSWIDTH_16.

Check also nand_set_defaults, make sure busw is not 0x2. Make sure chip->read_byte = nand_read_byte."

In drivers/mtd/nand/ti81xx_nand.c

board_nand_init()
{............
/* If we are 16 bit dev, our gpmc config tells us that */
if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) {
printf("DM385 -> GPMC setting to x16 bit\n");
nand->options |= NAND_BUSWIDTH_16;
}
printf("DM385 -> GPMC setting to x8 bit\n");
........
}

In drivers/mtd/nand/nand_base.c

static void nand_set_defaults(struct nand_chip *chip, int busw)
{....
if (!chip->read_byte)
{
printf("DM385 -> BUSW : %d\n",busw);
chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
}
......
}

NAND: Searching for NAND device @ GPMC CS:0
DM385 -> GPMC setting to x8 bit
HW ECC BCH8 Selected
DM385 -> BUSW : 0
0 MiB

0x50000060 : 0x800
0x48140040 : 0x317

But still it has not detected. i checked patch also but that is of no help.

regards,
Ganesh

I will notify the IPNC RDK team for help. Hope they have s.th. to share.

Regards,
Pavel

Hi Pavel Botev ,

sorry for late reply as NAND suport was taking lot of time i was busy on other issues of my project, can you tell me is their any input available from IPNC RDK team, even my senior are busy with other aspect of project. i'm looking into the NAND support now so it will be helpful if can get some information.

regards,
Ganesh

Hi Ganesh,


I have already provide you all the info I have. The linux/u-boot NAND driver is working fine, I have proven this on my side. The problem is most probably related to HW malfunction. We do not provide schematic and PCB layout review over the e2e forum. For this you will need to contact your local TI representative/FAE.

The IPNC RDK team is notified. If they have something, they will write here directly in this e2e thread.

Regards,
Pavel

Hi Pavel Botev ,
Is it possible for you too send me MLO and uboot.bin file which you have tested on your evm board i just want to test it.

regards,
Ganesh

Ganesh,

I tested on DM814x TI EVM, with the pre-built MLO and u-boot.bin, available at the EZSDK 5.05.02.00

ti-ezsdk_dm814x-evm_5_05_02_00/board-support/prebuilt-images/

You can get the EZSDK from the below link.

software-dl.ti.com/.../index_FDS.html

Regards,
Pavel