DRA75x DDR3 : 3GB DDR support on DRA75x/74x

Yasuhiro Mitsui

Expert 6390 points

Customer want to connect 3GB memory to Jacinto6.

So, below configuration is able to use ?

EMIF1 8Gbit-DDR3 (x16) x 2 chips : 2GByte(32bit width)

EMIF2 4Gbit-DDR3 (x16) x 2 chips : 1GByte(32bit width)

We have following in Data Manual, so above configuration has no problem.

• 16-bit or 32-bit data path to external SDRAM memory

• Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices (Single die only)

• One interface with associated DDR2/DDR3 PHYs

But not mentioned that connect different capacity for each EMIF is OK or not.

So, I would like to confirm.

Yes, they uses interleave for only 2GB aria.

Best Regards,

Yasuhiro Mitsui

over 9 years ago

0 Dobrin Dobrinov over 9 years ago

TI__Intellectual 2330 points

Hi Mitsui-san,

I think it's possible. I couldn't find any restrictions indicating the above configuration is not possible. However, you should take into account the following:

The DMM_LISA_MAP_i registers are configured to enable interleaving.
The MA_LISA_MAP_i registers are configured with the same settings as DMM_LISA_MAP_i.
The upper 1GB of EMIF1 will be accessible only by the MPU as 2GB is the maximum memory capacity shared among the system (in your case interleaved on EMIF1 and EMIF2).
The high-order fixed interleaving of the MPU_MA must be disabled by keeping the MA_PRIORITY[8] HIMEM_INTERLEAVE_UN bit to its reset value of 0x0.
The upper 1GB of EMIF1 will be accessible by the MPU at address range Q8.
There is also the following statement in the TRM: "Heavy use in high memory space under noninterleaved configuration affects the balancing of the system access in lower-order memory."
The MPU_MA Firewall (MA_MPU_NTTP_FW) must be properly configured. I mean, to not block the MPU accesses to Q8.

In addition, I think different capacity for each EMIF is OK as the DMM TRM section shows an example of connecting 256MB to EMIF1 and 512MB to EMIF2 (512 MB interleaved and 256 MB noninterleaved). The exact section name is "15.2.4.2.2 Case 2: Use of Two Memory Controllers".

BR,

Dobrin

0 Yasuhiro Mitsui over 9 years ago in reply to Dobrin Dobrinov

TI__Expert 6390 points

Dobrin,

thanks.
I will tell it to customer.
if you get any additional info for the future, please let us know.

Best Regards,
Yasuhiro Mitsui

0 David Smalley over 9 years ago in reply to Yasuhiro Mitsui

TI__Expert 7210 points

Agree with Dobrins comments above.

One more datapoint re, un-equal memory capacity on EMIF1 and EMIF2 - The original J6 EVM had 0.5 GB on EMIF1 (2 pieces of 2 Gbit DDR3 arranged x16 wide plus another x8 device for ECC parity) and 1.0 GB on EMIF2 (4 pieces of 2 Gbit DDR3 arranged x8 wide) so this is not a problem.

Be aware of the SW impact using more than 2GB since the OS needs to use LPAE modes for ARM core to access above 2 GB. Also, other chip resources (other cores and DMAs) cannot access the space above 2GB so the operating system must take this into account.

0 Yasuhiro Mitsui over 9 years ago in reply to David Smalley

TI__Expert 6390 points

David,

thank you for your info.
I only checked latest CPU board Users Guide which mentioned below.

Memory:
– EMIF1 - DDR3L-1066 (with ECC): two 8Gbit (16bit data/ea) and one 4Gbit (8bit data, for ECC) memory devices
– EMIF2 - DDR3L-1066: four 4Gbit (8bit data/ea) memory devices

In fact, old one mentioned below.

Memory:
– EMIF1 - DDR3L-1066 (with ECC): two 2Gbit (16bit data/ea) and one 1Gbit (8bit data, for ECC) memory devices
– EMIF2 - DDR3L-1066: four 2Gbit (8bit data/ea) memory devices

Best Regards,
Yasuhiro Mitsui

0 ya lin over 8 years ago in reply to Yasuhiro Mitsui

Intellectual 840 points

Hi Yasuhiro Mitsui:

Where can I find the guide of dra7xx DDR leveling through CCS？
Whether there is any alternative to do DDR leveling?

Ya Lin

0 Dobrin Dobrinov over 8 years ago in reply to ya lin

TI__Intellectual 2330 points

Hi Ya Lin,

1. The leveling code is part of the EMIF initialization sequence that is executed each time when connecting to a target thru CCS. The init sequence resides in a .gel file. On my Windows machine the path to that gel file is as follows:
C:\ti\ccsv6\ccs_base\emulation\gel\DRA75x_DRA74x\DRA7xx_ddr_config.gel

2. If you route the DDR3 interface on your board using fly-by topology there is no alternative to leveling. I mean, you have to use leveling. If you don't want to use leveling you have to use the balanced-T routing scheme typical for DDR2.

BR,
Dobrin

0 ya lin over 8 years ago in reply to Dobrin Dobrinov

Intellectual 840 points

HI Dobrin
follow your instruction I found out the gel file. but I am not able to find the ccs binary file to run DDR software leveling.
I expect the binary file just like DDR3_slave_ratio_search_auto.out on am335x platform.
processors.wiki.ti.com/.../Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack

Ya Lin

0 Dobrin Dobrinov over 8 years ago in reply to ya lin

TI__Intellectual 2330 points

Hi Ya Lin,

Now I understood what you want. I don't know if such a file exists as TI recommends to use HW instead of SW leveling. During HW leveling the tuning procedure is performed automatically by the DDR3 PHY. I'll ask and let you know if there is a file similar to DDR3_slave_ratio_search_auto.out.

BR,
Dobrin

0 Pavel Botev over 8 years ago in reply to ya lin

TI__Guru**** 170625 points

Ya Lin,

There is "Vayu_DDR_configuration" package that has some info regarding DDR3. But it is available on internal server and you can get it under NDA through local TI FAE. Pass your FAE the below link:
cdds.ext.ti.com/.../emxNavigator.jsp

We have something similar in public regarding AM57x DDR:
www.ti.com/.../sprac36.pdf

Regards,
Pavel

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DRA75x DDR3 : 3GB DDR support on DRA75x/74x