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DM37xx SYS_CLKREQ request with PER Active query

Raviraj Somnache1
Intellectual 430 points
Other Parts Discussed in Thread: DM3725

Hi All,

We are using DM3725 and working on power management on RTOS with our own BSP.

We are able to go to retention and SYS_CLKREQ pin in going low and 26MHz system clocking switching off, also wakeup is also working fine.

But as per our design we need to GP timer 5 to be active which is configured for 32KHz clock, in this we are not switching off GPtimer 5 functional clock because GP timer5 wakeup is required for our system.

So with this PER active state(other all power domains are in retention)  SYS_CLKREQ  is not going low and 26MHz clock is active.

Can you please let us know how we can switch off system clock in GPtimer5 wakeup enable state?

Is system clock to switch off all domains required to go in retention?

What is this Sleep state and how we can configure PER in sleep state where we can wakeup from GP timer 5.

Please add your suggestions/comments to resolve this issue.

Thanks,

Raviraj

  • 0
    Intellectual 430 points
    Please anyone help us on this.

    Thanks,
    Raviraj
  • 0
    TI__Guru 65405 points
    Hi Raviraj,

    Could you check the value of MSuspend Control register CONTROL_MSUSPENDMUX_1[23:21] GPTM5MSCTRL which Controls General Purpose Timer 5 sensitivity to MCU and/or DSP MSuspend signals. If the value of GPTM5MSCTRL field is 0x0 change it to 0x5.
    You can select the source of GPTIMER 5 source clock byCM_CLKSEL_PER[3] CLKSEL_GPT5 register field (0x0 32K_FCLK or 0x1 SYS_CLK).
    Also check the GPTIMER 5 auto clock control field CM_AUTOIDLE_PER[6] AUTO_GPT5.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    Intellectual 430 points
    Thanks for inputs, this fix is very much important for our product.
    We verified CONTROL_MSUSPENDMUX_1[23:21] register value and it was 0x0 we tried by setting 0x05 with CM_CLKSEL_PER[3] = 0 and CM_AUTOIDLE_PER[6] =1. But still PER is in active state and SYS_CLKREQ signal not going down.
    In this we are not disabling GPtimer5 functional clock which is configured to 32KHz.

    Our requirement is GPtimer5 should be able to wakeup system from retention state(in which 26MHz system clock is switch off).

    Is it possible to PER to put in retention state if GPtimer5 32KHz function clock is active?
    Is it possible to switch off SYS_CLKREQ if GPtimer5 32KHz function clock is active?


    Thanks,
    Raviraj
  • 0 in reply to Raviraj Somnache1
    Intellectual 430 points
    Hi Tsvetolin Shulev,
    Can you please provide your inputs on this, this will unblock and will help us to take major design decision.

    Thanks,
    Raviraj
  • 0 in reply to Raviraj Somnache1
    TI__Guru*** 125430 points
    How is TIOCP_CFG configured for GPTimer5? Have you tried configuring CLOCKACTIVITY=2 (ICLK off, FCLK on)?

    Can you also check CM_IDLEST_PER for the good case vs bad case?

    When you say "retention" can you specify what exactly you are doing, i.e. are you adjusting voltages or just trying to gate as many clocks as possible?
  • 0 in reply to Brad Griffis
    TI__Guru*** 125430 points
    PS. Any reason you're not using GPTimer1 for this purpose? It's in WKUP domain, so that would allow you to cleanly put PER domain to retention.
  • 0 in reply to Brad Griffis
    Intellectual 430 points
    We tried with both TIOCP_CFG register CLOCKACTIVITY value 0 and 2 but in both this is not working.
    CM_IDLEST_PER register ST_GPT5 bit is 0.
    Retention means, all domains are in retention and switch off system clock 26MHz using SYS_CLKREQ signal.

    if we disable gptimer5 functional clock then able to go to retention, SYS_CLKREQ signal going low and 26MHz system clock is switching off.(which is expected).

    But in our product we need two independent timers(one for MCU and other for DSP[IVA]) which can run on 32KHz and wakeup MCU, DSP independently.

    Currently we are using GPtimer 1 for MCU and this is working fine for MCU to wakeup and same we required one more timer GPtimer5 which can run on 32KHz and wakeup IVA.


    Is it possible to configure GPtimer5 on 32KHz clock and put PER and CORE in retention and switch off system clock. And GPtimer can wakeup system after wakeup timeout.


    Thanks,
    Raviraj
  • 0 in reply to Raviraj Somnache1
    TI__Guru*** 125430 points

    Raviraj Somnache1 said:
    We tried with both TIOCP_CFG register CLOCKACTIVITY value 0 and 2 but in both this is not working.
    CM_IDLEST_PER register ST_GPT5 bit is 0.

    This unfortunately is what I was expecting, but I wanted to be absolutely sure...

    Raviraj Somnache1 said:
    Is it possible to configure GPtimer5 on 32KHz clock and put PER and CORE in retention and switch off system clock. And GPtimer can wakeup system after wakeup timeout.

    If you keep the GPTimer5 functional clock alive then that means the peripheral module is still active, and as a result you cannot transition the PER domain to retention.  For example, here's a snippet from the TRM discussing power domain transitions:

    • When all clocks are shut down in a power domain, transitions from inactive-to-off or inactive-to-retention can occur.

    Raviraj Somnache1 said:
    Currently we are using GPtimer 1 for MCU and this is working fine for MCU to wakeup and same we required one more timer GPtimer5 which can run on 32KHz and wakeup IVA.

    I suggest getting an external timer that can wakeup the DSP through a pin associated with GPIO1.  Since GPIO1 is part of the WKUP domain that would enable you to completely disable the PER domain and still wake up.

  • 0 in reply to Brad Griffis
    Intellectual 430 points
    Thanks for your inputs.
    I am just thinking GPtimer5 is configured on 32KHz then why system clock is required and not cutting off also why PER and system is not going into retention.

    We have already tested with external TCXO chip which is running on 32KHz clock and able to wakeup on GPIO1 bank gpio.

    We wanted to verify whether GPtimer5 wakeup with 32KHz in retention with system clock off supported by TI chip or not, Or we are missing some configuration before modifying our HW and before going for production.

    With your input it is confirmed that it is not supported and now we can go with external 32KHz chip wakeup design for next Spin production.

    Thanks for your inputs.

    Raviraj
  • 0 in reply to Raviraj Somnache1
    TI__Guru*** 125430 points

    Raviraj Somnache1 said:
    I am just thinking GPtimer5 is configured on 32KHz then why system clock is required and not cutting off also why PER and system is not going into retention.

    If the GPTimer5 functional clock is enabled (32k clock) then by definition GPTimer5 is active.  The PER domain cannot achieve any low power modes while any modules are active.  It's a cascading effect, i.e. GPTimer5 active causes PER to stay on which causes the system clock to stay on.

    Raviraj Somnache1 said:
    We have already tested with external TCXO chip which is running on 32KHz clock and able to wakeup on GPIO1 bank gpio.

    Raviraj Somnache1 said:
    With your input it is confirmed that it is not supported and now we can go with external 32KHz chip wakeup design for next Spin production.

    I'm glad to hear you can spin the board quickly to get passed the issue!

  • 0 in reply to Brad Griffis
    Intellectual 430 points
    Yes for testing purpose we have modified our current spin board and with that verified external TCXO chip configuration and wakeup, same we will modified in next Spin schematic and PCB which will go to final production.

    Once again thanks for your inputs.

    -Raviraj