EVMK2H DDR3 Boot Parameter Table

HS Park

Hi Experts,

I create a DDR3 boot parameter table for EVMK2H by referring to files below:
- c:\ti\ccsv6\ccs_base\emulation\boards\xtcievmk2x\gel\xtcievmk2x.gel
- SPRS866E (Multicore DSP+ARM KeyStone II System-on-Chip)

But, it seems that DDR3 is not initialized after boot. I checked the DDR3 boot parameter table is loaded at 0x008ffd20.

Here is DDR3 boot parameter table I created. Please check where I mistook.

Or if you can, please send me DDR3 boot parameter table for EVMK2H.

const BOOT_EMIF4_TBL_T  emif4Cfg =  {

/* Config select MSW  */
(1<<0) | (1<<1) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) | (1<<14),
    
/* Config select SLSW  */
(1<<1) | (1<<3) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | (1<<11) | (1<<17) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23) | (1<<26),
    
/* Config select LSW  */
(1<<3),
            
/* 0*/	1,	/* pllPrediv */
/* 0*/	20,	/* pllMult */
/* 0*/	6, 	/* pllPostDiv */
     
/* 1*/	0x62009C62, /* sdRamConfig */
/* 2*/	0,	            /* sdRamConfig2 */
/* 3*/	0x00001457, /* sdRamRefreshCtl */
/* 4*/	0x125C8044, /* sdRamTiming1 */
/* 5*/	0x00001D29, /* sdRamTiming2 */
/* 6*/	0x32CDFF43, /* sdRamTiming3 */
/* 7*/	0x543F0ADF, /* sdRamTiming4 */
/* 8*/	0,                  /* powerManageCtl */

/* 9*/	 0,          /* iODFTTestLogic */
/*10*/ 0,          /* performCountCfg */
/*11*/	 0,          /*performCountMstRegSel */
	
/*12*/ 0,	/* readIdleCtl */
/*13*/ 0,	/* sysVbusmIntEnSet */
/*14*/ 0x70073200,	/* sdRamOutImpdedCalCfg */
/*15*/ 0,		/* tempAlterCfg */
/*16*/ 0,		/* ddrPhyCtl1 */
/*17*/ 0,		/* ddrPhyCtl2 */

/*18*/ 0,              /* priClassSvceMap */
/*19*/ 0,              /* mstId2ClsSvce1Map */
/*20*/ 0,              /* mstId2ClsSvce2Map */
/*21*/ 0,              /* eccCtl */
/*22*/ 0,              /* eccRange1 */
/*23*/ 0,              /* eccRange2 */
/*24*/ 0,              /*rdWrtExcThresh */



/* 0*/	0,
/* 1*/	0x00000033,    /* DDR3A_PIR */
/* 2*/	0,                    /* DDR3A_PGCR0 */
/* 3*/	0x0280C4A5,   /* DDR3A_PGCR1 */
/* 4*/	0,                    /*DDR3A_PGSR0*/
/* 5*/	0,                    /*DDR3A_PGSR1*/
/* 6*/	0x5C000,         /*DDR3A_PLLCR*/
/* 7*/	0x42C21590,   /* DDR3A_PTR0 */
/* 8*/	0xD05612C0,   /* DDR3A_PTR1 */
/* 9*/	0,
/*10*/ 0x0B4515C2, /* DDR3A_PTR3 */
/*11*/	 0x0A6E08B4, /* DDR3A_PTR4 */
/*12*/ 0,
/*13*/ 0,
/*14*/ 0,
/*15*/ 0,
/*16*/ 0,
/*17*/ 0x0000040B, /* DDR3A_DCR */
/*18*/ 0x8558AA75, /* DDR3A_DTPR0 */
/*19*/ 0x32857280, /* DDR3A_DTPR1 */
/*20*/ 0x5002C200, /* DDR3A_DTPR2 */
/*21*/ 0x00001A60, /* DDR3A_MR0 */
/*22*/ 0x00000006, /* DDR3A_MR1 */
/*23*/ 0x00000010, /* DDR3A_MR2 */
/*24*/ 0,
/*25*/ 0,
/*26*/ 0x710035C7, /* DDR3A_DTCR */
/*27*/ 0,
/*28*/ 0,
/*29*/ 0,
/*30*/ 0,
/*31*/ 0,

/* 0*/	0,
/* 1*/	0,
/* 2*/	0,
/* 3*/	0x00F065B8, /* DDR3A_PGCR2 */
/*..*/	0,
};

Best regards,

HS.

over 8 years ago

0 Cvetolin Shulev-XID over 8 years ago

TI__Guru 65405 points

Hi HS,

I've forwarded this to the DDR3 experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

0 Rahul Prabhu over 8 years ago

TI__Guru** 116020 points

HS,

Here is the DDR boot parameter table that we have been able to use in the past to validate DDR initialization using the bootROM.

/* ------------------------------------------------------------------------
 * DDR3 configuration. This const section must be loaded first so that 
 *    the code loaded to DDR3 will work
 * ------------------------------------------------------------------------ */
#pragma  DATA_SECTION (emif4Cfg, ".emif4Cfg")
const BOOT_EMIF4V_TBL_T  emif4Cfg =  {

    /* Config select msw */
    BOOT_EMIF4V_ENABLE_MSW_pllCtl          | \
    BOOT_EMIF4V_ENABLE_MSW_sdRamTiming1    | \
    BOOT_EMIF4V_ENABLE_MSW_sdRamTiming2    | \
    BOOT_EMIF4V_ENABLE_MSW_sdRamTiming3    | \
    BOOT_EMIF4V_ENABLE_MSW_sdRamTiming4    | \
    BOOT_EMIF4V_ENABLE_MSW_sdRamRefreshCtl | \
    BOOT_EMIF4V_ENABLE_MSW_zqConfig        | \
    BOOT_EMIF4V_ENABLE_MSW_sdRamConfig,

    /* Config select slsw */
    (1 << BOOT_EMIF4V_DWCPUB_PTR0)         | \
    (1 << BOOT_EMIF4V_DWCPUB_PTR1)         | \
    (1 << BOOT_EMIF4V_DWCPUB_PTR3)         | \
    (1 << BOOT_EMIF4V_DWCPUB_PTR4)         | \
    (1 << BOOT_EMIF4V_DWCPUB_MR0)          | \
    (1 << BOOT_EMIF4V_DWCPUB_MR1)          | \
    (1 << BOOT_EMIF4V_DWCPUB_MR2)          | \
    (1 << BOOT_EMIF4V_DWCPUB_DTCR)         | \
    (1 << BOOT_EMIF4V_DWCPUB_PGCR1)        | \
    (1 << BOOT_EMIF4V_DWCPUB_PGCR2)        | \
    (1 << BOOT_EMIF4V_DWCPUB_PIR)          | \
    (1 << BOOT_EMIF4V_DWCPUB_DCR)          | \
    (1 << BOOT_EMIF4V_DWCPUB_DTPR0)        | \
    (1 << BOOT_EMIF4V_DWCPUB_DTPR1)        | \
    (1 << BOOT_EMIF4V_DWCPUB_DTPR2)        | \
    (1 << BOOT_EMIF4V_DWCPUB_PLLCR)        | \
    (1 << BOOT_EMIF4V_DWCPUB_ZQ0CR1)       | \
    (1 << BOOT_EMIF4V_DWCPUB_ZQ1CR1)       | \
    (1 << BOOT_EMIF4V_DWCPUB_ZQ2CR1),
    

    0,      /* Config select lsw  */
    
    1,      /* pllPrediv  */
    20,     /* pllMult    */
    6,      /* pllPostDiv */

    0x62008c6a,  /* sdRamConfig */
    0x00001457,  /* sdRamRefreshCtl  */
    0x125c8044,  /* sdRamTiming1 */
    0x00001d29,  /* sdRamTiming2 */
    0x32cdff43,  /* sdRamTiming3 */
    0x543f0adf,  /* sdRamTiming4 */

    0,           /* powerManageCtl, dont care */
    0,           /* vbusmCfg */
    0,           /* vbusmCfgVal1 */
    0,           /* vbusmCfgVal2 */
    0,           /* iODFTTestLogic, dont care */
    0,           /* performCountCfg, dont care */
    0,           /* performCountMstRegSel, dont care */
    0x70073200,  /* zqConfig */

    0,           /* priClassSvceMap, dont care */
    0,           /* mstId2ClsSvce1Map, dont care */
    0,           /* mstId2ClsSvce2Map, dont care */
    0,           /* eccCtl, dont care */
    0,           /* eccRange1, dont care */
    0,           /* eccRange2, dont care */
    0,           /* rdWrtExcThresh, dont care */

    /* Phy registers */
    0x0000ff81,  /* PIR */
    0,           /* PGC0 */
    0x0280c485,  /* PGCR1 */
    0x00f065b8,  /* PGCR2 */
    0,           /* PGSR0 */
    0,           /* PGSR1 */
    0x42c21590,  /* PTR0 */
    0xd05612c0,  /* PTR1 */
    0,           /* PTR2 */
    0x0b4515c2,  /* PTR3 */
    0x0a6e08b4,  /* PTR4 */
    (1 <<10) | (1 << 27) | (1 << 29) | 0xb, /* DCR */
    0x8558aa55,  /* DTPR0 */
    0x12857280,  /* DTPR1 */
    0x5002c200,  /* DTPR2 */
    0x00001a60,  /* MR0 */
    0x00000006,  /* MR1 */
    0x00000010,  /* MR2 */
    0x730035c7,  /* DTCR */
    0,           /* DX0GCR */
    0,           /* DX1GCR */
    0,           /* DX2GCR */
    0,           /* DX3GCR */
    0,           /* DX4GCR */
    0,           /* DX5GCR */
    0,           /* DX6GCR */
    0,           /* DX7GCR */
    0,           /* DX8GCR */
    0x0005c000,  /* PLLCR  */
    0x0000005d,  /* ZQ0CR1 */
    0x0000005b,  /* ZQ1CR1 */
    0x0000005b,  /* ZQ2CR1 */


    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0
};

The BOOT_EMIFA macros are as defined in the tiboot.h file provided below:0116.tiboot.h

Hope this helps.

Regards,

Rahul

0 HS Park over 8 years ago in reply to Rahul Prabhu

Prodigy 180 points

HI Rahul,

Thank you for your reply.

But the structure format of BOOT_EMIF4V_TBL_T you sent to me is slightly different with Table 8-26 in SPRS866E.
Which format should I use.

0 Rahul Prabhu over 8 years ago in reply to HS Park

TI__Guru** 116020 points

HS,

The DDR configuration table in the datasheet seems to be copied over from the Keystone I device and needs to be updated. There is a literature bug pending on that document to update that table. The DDR structure BOOT_EMIF4V_TBL_T from the tiboot.h that I have provided is the one that needs to be used on Keystone II devices.

Regards,
Rahul

Processors

Processors forum

EVMK2H DDR3 Boot Parameter Table