Linux/TLV320AIC3106: Unable to sync register issue

Hi,

Can you please let me know what is the McASP0 pinmux register?

Sorry for bothering you!!


Thanks

Do you need the value of mcasp0_pins address in the device tree?

deep ter said:

Can you please let me know what is the McASP0 pinmux register?

We already discussed which are the McASP0 pinmux registers, but here they are one more time:

conf_gpmc_a8/0x44E10860

conf_gpmc_a9/0x44E10864

conf_gpmc_a10/0x44E10868

conf_gpmc_a11/0x44E1086C

Regards,
Pavel

deep ter said:

Do you need the value of mcasp0_pins address in the device tree?

No, I do not.

What I need are the values of the McASP0 pinmux registers in user space (take them with devmem2 tool) and in linux kernel (at mcasp_start_tx())

Regards,
Pavel

HI Pavel

Below is the result of pinmux registers with devmem2 and mcasp_start_tx

oot@ngt:~# Playing WAVE 'audiocheck1_10th_copy_converted.wav' : [ 37.591775] *********Entered davinci_mcasp_set_dai_fmt()1*************
Signed 16 bit Little Endian, Rate 44100 Hz, Stereo
[ 37.599383] *********Entered davinci_mcasp_set_dai_fmt()2*************
[ 37.610551] *********SND_SOC_DAIFMT_DSP_B************
[ 37.615646] *********SND_SOC_DAIFMT_AC97*************
[ 37.620719] ************case SND_SOC_DAIFMT_CBM_CFM************
[ 37.626679] ************case SND_SOC_DAIFMT_IB_NF************
[ 37.632768] **********The bias level is********1
[ 37.637497] **********Function is =********aic3x_set_power
[ 37.643027] *****Inside the func regcache_sync*****
[ 37.648184] tlv320aic3x-codec 1-001b: Unable to sync registers 0x1-0x1. -121
[ 37.655302] **********The bias level is********2
[ 37.661115] **********The bias level is********3
[ 37.674679] *******0x44e10860 is 26
[ 37.677599] ****0x44e10864**** 26
[ 37.680924] ****0x44e10868**** 6
[ 37.684162] ****0x44e1086C**** 26

root@ngt:~# devmem2 0x44E10860
/dev/mem opened.
Memory mapped at address 0xb6f50000.
Read at address 0x44E10860 (0xb6f50860): 0x00000026
root@ngt:~# devmem2 0x44E10864
/dev/mem opened.
Memory mapped at address 0xb6f2d000.
Read at address 0x44E10864 (0xb6f2d864): 0x00000026
root@ngt:~# devmem2 0x44E10868
/dev/mem opened.
Memory mapped at address 0xb6efc000.
Read at address 0x44E10868 (0xb6efc868): 0x00000006
root@ngt:~# devmem2 0x44E1086c
/dev/mem opened.
Memory mapped at address 0xb6fd1000.
Read at address 0x44E1086C (0xb6fd186c): 0x00000026
root@ngt:~# aplay: pcm_write:1737: write error: Input/output error

deep ter said:

[ 37.674679] *******0x44e10860 is 26
[ 37.677599] ****0x44e10864**** 26
[ 37.680924] ****0x44e10868**** 6
[ 37.684162] ****0x44e1086C**** 26

McASP0 pinmux seems to be correct now.

What I can suggest you next is:

- make McASP0 module registers dump in working case (previous sdk) and non-working case (this sdk), compare the result

- check AIC3x RESET pin with scope, compare the waveform between working case and non-working case

- check AIC3x MCLK, BCLK, WCLK, DIN, DOUT pins, compare the waveforms between working case and non-working case

- check AIC3x I2C pins, compare the waveforms between working case and non-working case

Hi Pavel,

Thanks for your suggestion.  One more concern from my observation:

I have added some printk in tlv320aic3x.c file.

In the function : aic3x_set_power()

The error  " Unable to Sync Register" is  coming from the file drivers/base/regmap/regcache.c . WE are getting the error from the function regcache_sync_block_raw_flush()

 

Thanks

Hi Pavel

I am also attaching my codec driver for review...Please let me know if I need to make any change.

7028.tlv320aic3x.c

deep ter said:

One more concern from my observation:

I have added some printk in tlv320aic3x.c file.

In the function : aic3x_set_power()

The error  " Unable to Sync Register" is  coming from the file drivers/base/regmap/regcache.c . WE are getting the error from the function regcache_sync_block_raw_flush()

From what I understand, the "unable to sync register" error comes when your flow goes in the aic3x_set_power() function, is that correct? In the if(power) or in else case your flow goes?

It seems to me that your AIC3x codec is not properly reset by the AM335x GPIO pin. Can you check this with the scope? See also the below e2e thread:

In AM335x TI EVM, the AIC3x codec is reset by the PMIC. As you do not have PMIC in your custom board, you should reset by GPIO pin.

Regards,
Pavel

deep ter said:

I am also attaching my codec driver for review...Please let me know if I need to make any change.

To port Audio driver in custom board, there is no need to change the AIC3x driver, see the wiki page below:

If you need to change the AIC3x codec driver, you should ask in the Audio codec forum.

Regards,
Pavel

Hi Pavel,

Thanks for suggestion. In the codec driver the codec-reset is being toggled. I checked with the scope. Also in the driver this is the piece of code in the probe :


if (gpio_is_valid(aic3x->gpio_reset) &&
!aic3x_is_shared_reset(aic3x)) {
ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
if (ret != 0)
goto err;
gpio_direction_output(aic3x->gpio_reset, 0);
udelay(10) ;
gpio_direction_output(aic3x->gpio_reset,1 );


But there is one big issue. I am not getting anything on BITCLK,WCLK ,DIN and DOUT while playing a song. I checked on the scope

deep ter said:

Thanks for suggestion. In the codec driver the codec-reset is being toggled. I checked with the scope. Also in the driver this is the piece of code in the probe :


if (gpio_is_valid(aic3x->gpio_reset) &&
!aic3x_is_shared_reset(aic3x)) {
ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
if (ret != 0)
goto err;
gpio_direction_output(aic3x->gpio_reset, 0);
udelay(10) ;
gpio_direction_output(aic3x->gpio_reset,1 );

Do you mean AIC3x codec RESETn (pin 33) toggles at the same time and with the same duration as in SDK7?

deep ter said:

But there is one big issue. I am not getting anything on BITCLK,WCLK ,DIN and DOUT while playing a song. I checked on the scope

Please provide me McASP0 module register dump for both cases (working and non-working).

Regards,
Pavel

Hi Pavel,

Yes, In both the drivers codec reset happens at the same time. So this cannot be the issue.

I am sending the Mcasp0 register Dump of PDIN, PDOUT.PFUNC Registers

Non-working:

root@ngt:~# aplay audiocheck1_10th_copy_converted.wav

aplay: /usr/lib/libasound.so.2: no version information available (required by aplay)

aplay: /usr/lib/libasound.so.2: no version information available (required by aplay)

aplay: /usr/lib/libasound.so.2: no version information available (required by aplay)

Playing WAVE 'audiocheck1_10th_copy_converted.wav' : [   19.940636] *********Entered davinci_mcasp_set_dai_fmt()1*************

Signed 16 bit Little Endian, Rate 44100 Hz, Stereo

[   19.948325] *********Entered davinci_mcasp_set_dai_fmt()2*************

[   19.959230] *********SND_SOC_DAIFMT_DSP_B************

[   19.964300] *********SND_SOC_DAIFMT_AC97*************

[   19.969386] ************case SND_SOC_DAIFMT_CBM_CFM************

[   19.975342] ************case SND_SOC_DAIFMT_IB_NF************

[   19.981430] **********The bias level is********1

[   19.986156] **********Function is =aic3x_set_power

[   19.990988] *****Inside the func regcache_sync*****

[   19.996142] tlv320aic3x-codec 1-001b: Unable to sync registers  2 0x1-0x1. -121

[   20.003492] ****pLL is set***

[   20.006501] **********The bias level is********2

[   20.012317] **********The bias level is********3

[   20.025932] 0x44e10860 is 6

[   20.028765] ****0x44e10864**** 6

[   20.032004] ****0x44e10868**** 6

[   20.035242] ****0x44e1086C**** 26

[   20.038571] Register with address 0x480380a0 is  DAVINCI_MCASP_GBLCTLX_REG 1f00

[   20.045908] Register with address 0x48038014 is PDIR Register  1

[   20.051938] Register with address 0x48038018 is PDOUT Register  0

[   20.058055] Register with address 0x4803801c is PDIN Register  0

Working :

In working SDK, prints are disabled, so I have taken the values using devmen2

root@ngt:~# aplay audiocheck1_10th_copy_converted.wav &
[1] 873
root@ngt:~# aplay: /usr/lib/libasound.so.2: no version information available (required by aplay)
aplay: /usr/lib/libasound.so.2: no version information available (required by aplay)
aplay: /usr/lib/libasound.so.2: no version information available (required by aplay)
Playing WAVE 'audiocheck1_10th_copy_converted.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo

root@ngt:~# devmem2 0x480380a0
/dev/mem opened.
Memory mapped at address 0xb6f04000.
Read at address  0x480380A0 (0xb6f040a0): 0x00001F00
root@ngt:~# devmem2 0x48038014
/dev/mem opened.
Memory mapped at address 0xb6f60000.
Read at address  0x48038014 (0xb6f60014): 0x08000001
root@ngt:~# devmem2 0x48038018
/dev/mem opened.
Memory mapped at address 0xb6fb5000.
Read at address  0x48038018 (0xb6fb5018): 0x00000000

root@ngt:~# devmem2 0x4803801C
/dev/mem opened.
Memory mapped at address 0xb6fb5000.
Read at address  0x48038018 (0xb6fb5018): 0x00000000

 

Thanks and Regards

Deep

deep ter said:

Yes, In both the drivers codec reset happens at the same time.

What about the duration of the reset signal? Is it the same?

deep ter said:

I am sending the Mcasp0 register Dump of PDIN, PDOUT.PFUNC Registers

I will have a look. Meanwhile you can send me the rest of the McASP0 module registers.

Regards,
Pavel

Hi Pavel,

If you can look in the logs of aplay  the control is getting inside SND_SOC_DAIFMT_CBM_CFM in davinci-mcasp.c

But in our case codec is slave and the BITCLOCK and LRCLK is generated from the processor.Wht is the control getting inside that case?

Are we missing any configuration?

Deep,

deep ter said:

[   19.969386] ************case SND_SOC_DAIFMT_CBM_CFM************

This means AIC3x codec is clock (BCLK) (ACLKX) and frame (WCLK) (AFSX) master. This is the default configuration, AM335x EVM and SK use this configuration.

deep ter said:

[   20.025932] 0x44e10860 is 6

[   20.028765] ****0x44e10864**** 6

These values mean mcasp0_aclkx and mcasp0_afsx are set is output (bit [5] is 0, RX disabled). What values you have in the McASP0 pinmux registers in the working case (SDK7)? Can you try to set mcasp0_aclkx and mcasp0_afsx as inputs (RX enable), the McASP0 should get BCLK and WCLK from the AIC3x codec, as the AIC3x codec is the master.

Regards,
Pavel

deep ter said:

If you can look in the logs of aplay  the control is getting inside SND_SOC_DAIFMT_CBM_CFM in davinci-mcasp.c

But in our case codec is slave and the BITCLOCK and LRCLK is generated from the processor.Wht is the control getting inside that case?

Are we missing any configuration?

This means AIC3x codec is clock (BCLK) (ACLKX) and frame (WCLK) (AFSX) master. This is the default configuration, AM335x EVM and SK use this configuration.

Try the below modification to configure AIC3x as slave, McASP0 as master:

am335x-boneblack.dts

simple-audio-card,bitclock-master = <&sound_master>;
simple-audio-card,frame-master = <&sound_master>;

sound_master: simple-audio-card,cpu {
                        sound-dai = <&mcasp0>;
                };

simple-audio-card,codec {
                        sound-dai = <&tlv320aic3106>;
            system-clock-frequency = <24000000>;
                };

Hi Pavel,

In working SDK7 mcasp0_aclkx and mcasp0_afsx were configured as i/P.

0x44e10860 is 26
0x44e10864 is 26
0x44e10868 is 6
0x44e1081C is 26

We have made the changes above as mentioned by you in the dts and the logs now which we are getting is

root@ngt:~# aplay audiocheck1_10th_copy_converted.wav

Playing WAVE 'audiocheck1_10th_copy_converted.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo[ 160.927752] *******The fmt = 4305

*********Entered davinci_mcasp_set_dai_fmt()1*************
[ 160.942976] *********Entered davinci_mcasp_set_dai_fmt()2*************
[ 160.949565] *********SND_SOC_DAIFMT_DSP_B************
[ 160.954636] *********SND_SOC_DAIFMT_AC97*************
[ 160.959722] ****SND_SOC_DAIFMT_MASTER_MASK is f000
[ 160.964530] ************case SND_SOC_DAIFMT_CBS_CFS************
[ 160.970487] ************case SND_SOC_DAIFMT_IB_NF************
[ 160.976289] davinci-mcasp 48038000.mcasp: Sample-rate is off by 400 PPM
[ 160.982931] *******Inside function __davinci_mcasp_set_clkdiv*****
[ 160.989149] ***********MCASP_CLKDIV_BCLK:*************
[ 160.994632] **********The bias level is********1
[ 160.999347] **********Function is =aic3x_set_power
[ 161.004176] *****Inside the func regcache_sync*****
[ 161.009338] tlv320aic3x-codec 1-001b: Unable to sync registers 2 0x1-0x1. -121
[ 161.016713] ****pLL is set***
[ 161.019693] **********The bias level is********2
[ 161.025510] **********The bias level is********3
[ 161.031297] 0x44e10860 is 6
[ 161.034122] ****0x44e10864**** 6
[ 161.037360] ****0x44e10868**** 6
[ 161.040599] ****0x44e1086C**** 26
[ 161.043926] Register 0x48038010 value PFUNC_REG 0
[ 161.048821] Register 0x48038014 value PDIR Register b4000001
[ 161.054676] Register 0x48038018 value PDOUT Register 0
[ 161.060007] Register 0x4803801c value PDIN Register 0
[ 161.065163] Register 0x48038020 value PDCLR Register 0
[ 161.070408] Register 0x48038044 value GBLCTL Register 200
[ 161.075913] Register 0x48038048 value AMUTE Register 0
[ 161.081158] Register 0x480380B0 value ACLKXCTL Register 180030
[ 161.087100] Register 0x480380B4 value AHCLKXCTL Register 0

aplay: pcm_write:1737: write error: Input/output error

Our current McASP0 Configuration is
mcasp0_pins: mcasp0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* mcasp0_aclkx*/
AM33XX_IOPAD(0x864, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* mcasp0_fsx*/
AM33XX_IOPAD(0x868, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* mcasp0_axr0*/
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE6) /* mcasp0_axr1 */
>;

deep ter said:

In working SDK7 mcasp0_aclkx and mcasp0_afsx were configured as i/P.

0x44e10860 is 26
0x44e10864 is 26
0x44e10868 is 6
0x44e1081C is 26

Does this mean that you were using AIC3x as master in SDK7, and now you are using AIC3x as slave in PSDK 3.2?

Severals things to check:

- you have 23.97MHz for the MCLK, check if you have the same in SDK7

 - compare the McASP0 module registers settings between SDK7 and PSDK3.2, check if there are any differences

- check I2C1 pins signals with scope, compare with SDK7

- check reset signal duration, compare with SDK7

Regards,
Pavel

Hi Pavel,

We have reverted our changes to Old SDK7. Now our Codec is Master.

->MCLK:  Same 24MHz both in Working and Non-working case.

-> McASP0 Module Register: A lot of differences in both Cases. I am putting them below.

Non Working:

Working:

-> I2C Signals:

This is one issue.

We are not getting SCL and SDA  when we are doing aplay.

The problem is that  eeprom is also  connected to the same I2C. We are able to access it.

This is unusual behaviour. What can be the issue?

-> Reset Signal

Working similar to SDK7

Thanks

Sorry The McASP0 Register dump was not attached:

> McASP0 Module Register: A lot of differences in both Cases. I am putting them below.

Non Working:

Working

deep ter said:

McASP0 Module Register: A lot of differences in both Cases. I am putting them below.

So now you are using AM335x as slave, AIC3x as master (in PSDK3.2)? You should use the default davinci-mcasp.c. Have you made any changes there?

Regards,
Pavel

deep ter said:

-> I2C Signals:

This is one issue.

We are not getting SCL and SDA  when we are doing aplay.

The problem is that  eeprom is also  connected to the same I2C. We are able to access it.

This is unusual behaviour. What can be the issue?

Do you have the same setup working fine with SDK7?

Regards,
Pavel

Hi Pavel,

Yes, You are right, We are using AM335X as a slave. But if you see McASP0 register in both working and Non-working case. THere is a lot of differences.

I have not made any changes in the davinci-mcasp driver.Its the default driver I am using. Only Additional printk I have done to check the register dump.

Also the same set up is working fine with SDK7.
We have just made pinmux enable for i2c1. That's it.

deep ter said:

I have not made any changes in the davinci-mcasp driver.Its the default driver I am using.

You are using the default davinci-mcasp driver for SDK7 or PSDK3.2?

I am using the default McASP driver in PSDK 3.2

What about SDK7, do you use the default davinci-mcasp.c driver there also?

Hi Pavel,

Yes We were using the default McASP Driver there also

Deep,

Let me summarize what we have so far.

You have AM335x custom board (based on BBB), McASP0 is slave, AIC3106 is master.

Audio is working fine in this board for SDK7 with the default mcasp driver.

Audio is not working fine in this board for PSDK3.2 with the default mcasp driver. And you see different McASP0 module registers settings between SDK7 and PSDK3.2

What you have change from the default PSDK3.2 are only two DTS files, is that correct? Can you attach the latest versions of your modified DTS files for review?

Regards,
Pavel

Hi Pavel,

Whatever you have mentioned above is correct.

I am sharing you the files

2626.am335x-boneblack.dts.txt

4073.am335x-bone-common.dtsi.txt

Hi Pavel,

In new SDK, device tree concept is present in Bootloader too along with Kernel and modules like i2c started working for us only after doing changes in the device tree of both bootloader as well as kernel.

Is there any dependency of mcasp or audio modules on bootloader device tree also?

Thanks
Deep

Deep,

I do not think u-boot audio setup impact kernel audio setup. We perform McASP and AIC3x reset in kernel, thus getting the default settings and then configure according to DTS and drivers.

I checked your DTS files, seems to be OK.

The first McAP register that differ between SDK7 and PSDK3.2 is the PDIR[27] AHCLKX bit. This bit is 0 (input) in SDK7 and 1 (output) in PSDK3.2.

The only place that PDIR[27] AHCLKX is set to 1 is in davinci-mcasp.c driver, davinci_mcasp_set_sysclk()

if (dir == SND_SOC_CLOCK_IN) {

...

} else {

mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);

 

Can you check your flow? Do you go in the else case where AHCLKX is set to 1?

Regards,

Pavel

Also GBLCTL value in PSDK3.2 shows that TX part is not active but is help in reset. This might be caused bu the RESETn signal issue or I2C configuration issue

Deep,

Glad to see it is fixed. So it was hardware issue after all.

Regards,
Pavel

Not a hardware issue exactly....just had to enable one gpio so that the buck regulator supply was enabled.