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AM5728: PCIe Gen2 link fails

matusan
Guru 10235 points
Part Number: AM5728

Hello, TI Experts,

 

We can get the detail from the customer about Gen2 link fail on AM5728 from the DK-san comment of E2E thread as below.

https://e2e.ti.com/support/arm/sitara_arm/f/791/p/596010/2222020#2222020

 

If three are some clue, please tell us.

 

<Detail>

 

- They use "3rd-party OS" and their custom board. (please refer attached pdf)

    - PCIE_SS1 connected to TI-USB Controller(TUSB7320IRKMT).

    - PCIE_SS2 connected to FPGA.

 

- They refer the sample code of PROCESSOR-SDK-RTOS-AM57X as below;

   C:\ti\pdk_am57xx_1_0_6\packages\ti\csl\example\pcie\write_loopback\rc\rc_write_loopback_app_main.c

 

Problem:

  PCIe GEN1-GEN2 switching Link to FPGA fails at PCIE initialization/link training phase as following.

    1: Link-up at Gen1 at PCIE initialization/link training phase.

    2: They want to switch to Gen2.

        So, they set the register value of PCIECTRL_TI_CONF_IRQSTATUS_RAW_MAIN.MAX_LINK_SPEEDS=0x2.

        Then, they set 0x1 to PCIECTRL_TI_CONF_DEVICE_CMD.LTSSM_EN.

        (reference: C:\ti\pdk_am57xx_1_0_6\packages\ti\csl\example\pcie\write_loopback\rc\rc_write_loopback_app_main.c)

    3: They found both OK & NG case.        

        OK: Gen2 switching is success.

        NG: Gen2 switching doesn’t happen.

                - Stay Gen1 ( they monitored PCIE main line signals by protocol analyzer.)

                - PCIECTRL_TI_CONF_IRQSTATUS_RAW_MAIN.LINK_REQ_RST seems to be set.

 

Key difference of OK case and NG case: (please refer attached pdf)

  - NG: They found "Ordered Set (Symbol Number4):Autonomous Change/Selectable De-emphasis=1" from FPGA on the protocol analyzer.

  - OK: They found "Ordered Set (Symbol Number4):Autonomous Change/Selectable De-emphasis=0" from FPGA on the protocol analyzer.

 

Questions:

   1) Do you have same experience or comment as below?

        - PCIE endpoint sent "Autonomous Change/Selectable De-emphasis" by "Ordered Set (Symbol Number4)"=1 to AM5728 as RootComplex.

        - After that,  PCIECTRL_TI_CONF_IRQSTATUS_RAW_MAIN.LINK_REQ_RST seems to be set (watched by polling this register address [0x51802020]).

           - They found the register result as below;

               - 0x51802020: LINK_REQ_RST=1, CFG_MSE_EVT=1, CFG_BME_EVT=1, LINK_UP_EVT=1;

               - 0X51802104: LTSSM_STATE[7:2]=0x00;

        - AM5728 also seems to be reset.

   2) Is there any restriction or notice of  "Autonomous Change / De-emphasis" function on AM5728?

  

We would appreciate if you tell us how to solve this problem.

 

Best regards,

PCIE_Gen2_fail.pdf

  • 0
    TI__Guru**** 393215 points
    The software team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points
    Hi,

    I am from the software side, let us work on the SW you used first, before reaching HW people for Ordered set. In your configuration, PCIE is used as two seperate lanes with each controller (SS1, SS2) one lane.

    On our TI EVMs (GP AM572x, IDK 572x, IDK571x) we only have either PCIESS1x1 lane or PCIESS1x2 lanes due to the PCIE connector limitation on the EVM. So, we don't have any test case showing how PCIE SS2x1 works but we helped customers with that configuration on their own board.

    From you description, you have PCIESS2x1 worked already. Can you tell me what code you referred to? There is some setting for B1C0 mode and how many lanes per controller for me to double check: You can dump register values for 0x4a002558 and 0x4a003c3c to me.

    Also, you mentioned that GEN1 works. I assume you did above correct. The way you switch GEN1 to GEN2 doesn't match our code. Please refer to pdk_am57xx_1_0_6\packages\ti\drv\pcie\example\sample\src\pcie_sample.c (that is, look at the PCIE driver code, not PCIE CSL code). Function pcieSetGen2():

    targetGen = 2;
    dirSpd = 1;

    Regards, Eric
  • 0 in reply to lding
    Guru 10235 points
    Hi,

    Thank you very much for your kindness.
    I really appreciate your help.
    I will get the additional information from the customer.

    Best regards,
  • 0 in reply to matusan
    Guru 10235 points
    Hi,

    Thank you very much for your kindness.
    I really appreciate your help.

    We got the detail about the register values from your request.
    　　address：0x4a002558　→ DATA：0x00000001
    　　address：0x4a003c3c　→ DATA：0x00000000

    We would appreciate if you tell us how to solve this problem.
    If there are any restriction or notice of "Autonomous Change / De-emphasis" function on AM5728, please also tell us.

    Best regards,
  • 0 in reply to matusan
    TI__Guru* 95265 points

    Hi,

    The register dumps looks right for PCIE SS1 and SS2 each controls a separate device. Do you have any failure rate statistics? Did GEN1 always work on PCIE SS2?

    In my previous update,

    targetGen = 2;

    dirSpd = 1;

    This is register PCIECTRL_PL_WIDTH_SPEED_CTL (0x5180_080c). Can you confirm if they tried this setting?

    For Autonomous Change / De-emphasis, I have no info, need look for it.

    Regards, Eric

  • 0 in reply to lding
    Guru 10235 points

    Hi,

    Thank you very much for your kindness.
    I really appreciate your help.


    I will confirm to the customer.

    And we are also waiting for the update about  some notice of "Autonomous Change / De-emphasis" function on AM5728 .

    Best regards,