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Hello!
I want to use uPP in full duplex mode with all 16 line count for transmit and receive. The pins for uPP XDATA[7..0] are multiplexing with BOOT[7..0] pins. How use the BOOT pin in this case? uPP is high speed interface, and external resistors for BOOT logic are bad for speed lines.
Thank you!
SOrry for the delayed response on this issue. Our current supported evaluation platform for this device doesn`t have a uPP interface so I had to dig through the archives to provide guidance on this topic.
The Boot mode pins are only used to latch the value of the bootmode at the time of power on reset so this pins default to BOOTMODE pin operation at the time of booting. Post boot you can setup the pinmux on the pins and use it for upp operation if required.
I believe the uPP interface was available on the LogicPD EVM through an extension connector for 16 line operation. you can look at the hw design files. Since the HW design files are available only to existinng registered users users of that evaluation platform, I am providing a link to the document here:
www.deyisupport.com/.../2211.aspx
I believe the same issue also exists for LCD users who need to use VPIF DOUT pins so I believe these pins are available post boot for peripheral operation.
Other reference design that use the uPP interface on this device is the MityDSP platform by Critical link. you could also refer to the HW design of their platform.
Regards,
Rahul
Thank's for your reply. I know, what I can use this pins after booting. But the speed of uPP port is near 75MHz. I think, that if I will use pullup and pulldown resistor for this speed lines on layout, this lines can don't work properly. Are was testing uPP lines combine with booting pins?
This document's has no information, what pins using for testing. In document writ, that using uPP channel 1. If using pins without BOOTMODE (UPP_D pins), I believing what uPP have this speed. But in document not describe, which pins group UPP_D or UPP_XD (multiplexing with BOOTMODE pins) are using for test...