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Linux/AM3352: USB eye diagram

Jian Zhou
Intellectual 1930 points
Part Number: AM3352

Tool/software: Linux

Hi expert,

Do we have the AM3352 USB eye diagram both on USB Host and USB device based on TI EVM such as BBB?

My customer tested the AM3352 USB eye diagram and feedback the signal is not good so I want to get some reference, thanks!

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0
    TI__Mastermind 27890 points

    Hello Jian,

    BBB is a community board and not a TI product so I will not have data for it. Typically, poor eye diagrams result from a failure to implement the interface as per TI requirements. Please review SPRAAR7 (TI High Speed Layout Guidelines) and ensure that the requirements contained within have been followed.

    I've attached both High-Speed Host and High-Speed Device eye diagrams from the TI AM335x General Purpose EVM.

  • 0 in reply to -DK-
    TI__Intellectual 1930 points
    Hi Dave,
    Thanks a lot for your support!
    As customer posted the USB eye diagram question during USB ESD test, could we get the AM335x USB layout guideline for ESD bypass from SPRAAR7? our do we have any other detailed guide for AM3352 USB ESD test?
  • 0 in reply to Jian Zhou
    TI__Mastermind 27890 points
    Jian,
    Yes, SPRAAR7 has an example of ESD bypass layout that is applicable to AM335x (or any other USB design).
  • 0 in reply to -DK-
    TI__Intellectual 1930 points

    Hi Dave,

    Thanks for your support!

    Customer show us the i.max 283 USB eye diagrams which is better than AM335x GPEVM as follows, and said i.max283 pass the USB ESD test which AM3352 board can not pass. The difference of PCB layout is that i.max283 USB line is just routed on the top layer but AM3352 USB line is routed on several layer both in GPEVM and customer's board. Could customer's AM3352 board get the same eye diagram by modifying the PCB layout based on the SPRAAR7 guide?

    I.max283 USB device eye diagram:

    i.max283 USB HOST eye diagram:

  • 0 in reply to Jian Zhou
    TI__Mastermind 27890 points
    Jian,
    I agree the top image, which appears to be Far End HS Eye, looks fine. I would disagree that the bottom image is good. Just from this image I can tell that there are significant jitter and impedance mismatch issues. These are very likely a result of a poor layout. You mention that there are several layer changes. These can contribute greatly to impedance mismatch issues if the vias are not handled correctly in the PCB design.

    TI recommends following best-practice high-speed layout practices, including those captured in SPRAAR7. AM335x has no issues passing USB compliance in a design that follows these guidelines.
  • 0 in reply to -DK-
    TI__Intellectual 1930 points

    Dave,

    Thanks for your support, I will also suggest customer to test the ESD on the AM3352 GPEVM.

  • 0 in reply to Jian Zhou
    TI__Intellectual 1930 points

    Dave,

    As some customers meet the AM3352 USB ESD test failure issue recently, besides the USB layout guide you provided, do you have any successful story on the USB ESD protection design?

    Thansk a lot!

  • 0 in reply to Jian Zhou
    TI__Mastermind 27890 points
    Jian,
    It seems that you are inquiring about USB ESD devices themselves rather than AM335x SoC. If so, please post those questions in the Circuit Protection forum as I am unable to comment on them here.

    e2e.ti.com/.../389