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c6747 floating point exception handling

Bill McKinney
Prodigy 235 points

Apologies, I know this has got to be documented somewhere, but I can't find it.  I'm trying to figure out how to trap NaN generation on the c6747.  I've found the discussion of the FADCR, FAUCR, and FMCR registers, but don't see a way to generate a trap based on these registers.  Where is that documented?

Thank you,

--Bill

 

  • 0
    TI__Guru*** 125430 points

    There's no interrupt, just a "sticky" status bit.  That is, once the bit gets set it stays set until software manually clears it.  They operate similar to how an overflow or saturation flag often operate, i.e. there is no interrupt but you can check the flags at any time.