RTOS/66AK2H14: 66AK2H14 Hyperlink issue with TMS320C6678

Nithin kumar24

Part Number: 66AK2H14

Tool/software: TI-RTOS

Hi All,

I'm using two 66AK2H14 processors in my custom board. Present status of the board is, able to bring up board and testing Hyperlink interface.

Two 66AK2H14 processors present in the board are connected via Hyperlink interface.

Hyperlink memory Mapped example is running successfully in LOOPBACK mode,But when I comment #define hyplnk_EXAMPLE_LOOPBACK and try to run between 2 66AK2H14 CCS is getting hang as below log

Version #: 0x02010007; string HYPLNK LLD Revision: 02.01.00.07:May 25 2018:11:00:09

About to do system setup (PLL, PSC, and DDR)

Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95

system setup worked

About to set up HyperLink Peripheral

============================Hyperlink Testing Port 0

========================================== begin registers before initialization ===========

Revision register contents:

Raw = 0x4e902101

Status register contents:

Raw = 0x00003004

Link status register contents:

Raw = 0x00000000

Control register contents:

Raw = 0x00000000

Control register contents:

Raw = 0x00000000

============== end registers before initialization ===========

Hyperlink Serdes Common Init Complete

Hyperlink Serdes Lane 0 Init Complete

Hyperlink Serdes Lane 1 Init Complete

Hyperlink Serdes Lane 2 Init Complete

Hyperlink Serdes Lane 3 Init Complete

============== begin registers after initialization ===========

Status register contents:

Raw = 0x04402005

Link status register contents:

Raw = 0xccf00cf0

Control register contents:

Raw = 0x00006204

============== end registers after initialization ===========

Waiting 5 seconds to check link stability

Analyzing the connection for each lane

Precursors 1

Postcursors: 19

Link seems stable

About to try to read remote registers..

I debugged step by step and got to know It was hanging at hyplnkExampleCheckOneStat (hyplnk_LOCATION_REMOTE, "after stability wait", 0);

What may be the issue with remote register read?

Please help me to solve this issue.

Regards,

Nithin

over 7 years ago

0 Yordan Kovachev over 7 years ago

TI__Guru**** 161600 points

Which RTOS sdk version are you using?

Best Regards,
Yordan

0 Nithin kumar24 over 7 years ago in reply to Yordan Kovachev

Intellectual 905 points

Hi Yordan,

I'm using "processor_sdk_rtos_k2hk_4_03_00_05" version.

Regards,
Nithin

0 Pavel Botev over 7 years ago in reply to Nithin kumar24

TI__Guru**** 170625 points

Nithin,

The issue seems to be related to ref clock speed and baud line rate. Refer to the below e2e threads for more info:

e2e.ti.com/.../332515
e2e.ti.com/.../1051743
e2e.ti.com/.../1022175

Regards,
Pavel

0 Nithin kumar24 over 7 years ago in reply to Pavel Botev

Intellectual 905 points

Hi Pavel,

Thanks for valuable input,
I selected "hyplnk_EXAMPLE_SERRATE_06p250" and with this Hyperlink0 is working for me.
I have Hyperlink1 connection between these two K2H14 processors as well. To test this interface I changed
"#define hyplnk_EXAMPLE_PORT 0" to "#define hyplnk_EXAMPLE_PORT 1" in "C:\ti\pdk_k2hk_4_0_9\packages\ti\drv\hyplnk\example\common\hyplnkLLDCfg.h" file and kept all other configurations same as Hyperlink0.
But with this change Hyperlink1 between two processors is not working. Console is hanged as below log

NON LOOPBACK!!!!!
Version #: 0x02010007; string HYPLNK LLD Revision: 02.01.00.07:May 25 2018:11:00:09
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000228; RX=0x0046c485; TX=0x000cc305
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 1
========================================== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e902101
Status register contents:
Raw = 0x00003004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========

Hyperlink Serdes Common Init Complete

Can you please let me know what change I have done is sufficient for Hyperlink1 interface testing??!

Regards,
Nithin

0 Nithin kumar24 over 7 years ago in reply to Nithin kumar24

Intellectual 905 points

Hi Pavel,

Any update on above issue ??!

Regards,

Nithin

0 Pavel Botev over 7 years ago in reply to Nithin kumar24

TI__Guru**** 170625 points

Nithin,

hyplnk_EXAMPLE_PORT change from 0 to 1 should be enough for using Hyperlink1.

Can you try memory mapped example in loopback mode for Hyperlink1? What is the result in this case?

Regards,
Pavel

0 Nithin kumar24 over 7 years ago in reply to Pavel Botev

Intellectual 905 points

Hi Pavel,

I run memory mapped example loopback test for Hyperlink1, it is running successfully. Please find log as below

Version #: 0x02010007; string HYPLNK LLD Revision: 02.01.00.07:May 25 2018:11:00:09
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000228; RX=0x0046c485; TX=0x000cc305
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 1
========================================== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e902101
Status register contents:
Raw = 0x00003004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
Hyperlink Serdes Common Init Complete
Hyperlink Serdes Lane 0 Init Complete
Hyperlink Serdes Lane 1 Init Complete
Hyperlink Serdes Lane 2 Init Complete
Hyperlink Serdes Lane 3 Init Complete
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04402005
Link status register contents:
Raw = 0xfdf0bdf0
Control register contents:
Raw = 0x00006206
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
Analyzing the connection for each lane
Precursors 0
Postcursors: 19
Link seems stable
About to try to read remote registers
============== begin REMOTE registers after initialization ===========
Status register contents:
Raw = 0x0440080f
Link status register contents:
Raw = 0xfdf0bdf0
Control register contents:
Raw = 0x00006202
============== end REMOTE registers after initialization ===========
Peripheral setup worked
About to read/write once
Single write test passed
About to pass 65536 tokens; iteration = 0
Link Speed is 4 * 6.25 Gbps

=== HyperLink results using CPU transfers ===
Passed 65536 tokens round trip (read+write through hyplnk) in 6522 Mcycles
Approximately 99523 cycles per round-trip
=== this is not an optimized example ===

=== HyperLink results using DMA transfers ===
Passed 65536 tokens round trip (read+write through hyplnk) in 424 Mcycles
Approximately 6475 cycles per round-trip
=== this is not an optimized example ===

=== HyperLink results using INFRA transfers ===
Passed 65536 tokens round trip (read+write through hyplnk) in 4034 Mcycles
Approximately 61558 cycles per round-trip
=== this is not an optimized example ===
Checking statistics
About to pass 65536 tokens; iteration = 1
Link Speed is 4 * 6.25 Gbps

=== HyperLink results using CPU transfers ===
Passed 65536 tokens round trip (read+write through hyplnk) in 6522 Mcycles
Approximately 99523 cycles per round-trip
=== this is not an optimized example ===

=== HyperLink results using DMA transfers ===
Passed 65536 tokens round trip (read+write through hyplnk) in 424 Mcycles
Approximately 6475 cycles per round-trip
=== this is not an optimized example ===

=== HyperLink results using INFRA transfers ===
Passed 65536 tokens round trip (read+write through hyplnk) in 4034 Mcycles
Approximately 61560 cycles per round-trip
=== this is not an optimized example ===
Checking statistics
About to pass 65536 tokens; iteration = 2
Link Speed is 4 * 6.25 Gbps

=== HyperLink results using CPU transfers ===
Passed 65536 tokens round trip (read+write through hyplnk) in 6522 Mcycles
Approximately 99523 cycles per round-trip
=== this is not an optimized example ===

=== HyperLink results using DMA transfers ===
Passed 65536 tokens round trip (read+write through hyplnk) in 424 Mcycles
Approximately 6475 cycles per round-trip
=== this is not an optimized example ===

=== HyperLink results using INFRA transfers ===
Passed 65536 tokens round trip (read+write through hyplnk) in 4034 Mcycles
Approximately 61561 cycles per round-trip
=== this is not an optimized example ===
Checking statistics
Hyperlink LLD Example Completed Successfully!

Regards,
Nithin

0 Pavel Botev over 7 years ago in reply to Nithin kumar24

TI__Guru**** 170625 points

Nithin,

I can suggest you to try several things:

- Make sure the both boards configuration match each other by checking PDK_INSTALL_DIR/packages/ti/drv/hyplnk/example/common/hyplnkLLDCfg.h. The default values are:
#define hyplnk_EXAMPLE_SERRATE_03p125
#define hyplnk_EXAMPLE_ALLOW_4_LANES

Make sure you have "#define hyplnk_EXAMPLE_PORT 1" in both boards hyplnkLLDCfg.h

- try with hyplnk_EXAMPLE_SERRATE_03p125 and hyplnk_EXAMPLE_SERRATE_01p250. You might have trace length limitation for Hyperlink1, thus need to use lower speed.

- check again you are using the correct hyperlink1 pins (transmit data, receive data, sideband signals).

I see also your teammate (from iwave systems) is double posting the same question and is being supported in the below e2e thread:

e2e.ti.com/.../693343

Regards,
Pavel

0 Nithin kumar24 over 7 years ago in reply to Pavel Botev

Intellectual 905 points

Hi Pavel,

I will try and let you know the results for suggestions given by you.

e2e thread posted by my team mate is related to Hyperlink0 loopback test failure case. This is resolved.

Now we are facing problem with hyperlink1 so I posted this new thread.

Regards,

Nithin

0 Nithin kumar24 over 7 years ago in reply to Nithin kumar24

Intellectual 905 points

Hi Pavel,

When we set "hyplnk_EXAMPLE_SERRATE_03p125" in code "hyplnkLLDConfig.h" file, link rate and lane rate are set as below

#elif defined hyplnk_EXAMPLE_SERRATE_03p125

linkRate = CSL_SERDES_LINK_RATE_6p25G;

lane_rate = CSL_SERDES_LANE_HALF_RATE;

#else

in this case log is as below

**** PDK SBL ****

SBL Revision: 01.00.09.00 (May 24 2018 - 15:21:24)

Begin parsing user application

Jumping to user application...

NON LOOPBACK!!!!!

Version #: 0x02010007; string HYPLNK LLD Revision: 02.01.00.07:May 25 2018:11:00:09

About to do system setup (PLL, PSC, and DDR)

Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95

system setup worked

About to set up HyperLink Peripheral

============================Hyperlink Testing Port 1

========================================== begin registers before initialization ===========

Revision register contents:

Raw = 0x4e902101

Status register contents:

Raw = 0x00003004

Link status register contents:

Raw = 0x00000000

Control register contents:

Raw = 0x00000000

Control register contents:

Raw = 0x00000000

============== end registers before initialization ===========

Hyperlink Serdes Common Init Complete

Hyperlink Serdes Lane 0 Init Complete

Hyperlink Serdes Lane 1 Init Complete

Hyperlink Serdes Lane 2 Init Complete

Hyperlink Serdes Lane 3 Init Complete

Waiting for other side to come up ( 0)

Waiting for other side to come up ( 1)

Waiting for other side to come up ( 2)

Waiting for other side to come up ( 3)

Waiting for other side to come up ( 4)

Waiting for other side to come up ( 5)

Waiting for other side to come up ( 6)

Waiting for other side to come up ( 7)

Waiting for other side to come up ( 8)

Waiting for other side to come up ( 9)

Waiting for other side to come up ( 10)

Waiting for other side to come up ( 11)

Waiting for other side to come up ( 12)

Waiting for other side to come up ( 13)

Waiting for other side to come up ( 14)

Waiting for other side to come up ( 15)

Waiting for other side to come up ( 16)

Waiting for other side to come up ( 17)

Waiting for other side to come up ( 18)

Waiting for other side to come up ( 19)

Waiting for other side to come up ( 20)

Waiting for other side to come up ( 21)

Waiting for other side to come up ( 22)

Waiting for other side to come up ( 23)

Waiting for other side to come up ( 24)

Waiting for other side to come up ( 25)

Waiting for other side to come up ( 26)

When we change linkrate to "linkRate = CSL_SERDES_LINK_RATE_3p125G;" in "hyplnkLLDIFace.c" we are getting log as below

Version #: 0x02010007; string HYPLNK LLD Revision: 02.01.00.07:May 25 2018:11:00:09

About to do system setup (PLL, PSC, and DDR)

Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95

system setup worked

About to set up HyperLink Peripheral

============================Hyperlink Testing Port 1

========================================== begin registers before initialization ===========

Revision register contents:

Raw = 0x4e902101

Status register contents:

Raw = 0x00003004

Link status register contents:

Raw = 0x00000000

Control register contents:

Raw = 0x00000000

Control register contents:

Raw = 0x00000000

============== end registers before initialization ===========

Invalid Serdes Init Params : 2

This is because, in "C:\ti\pdk_k2hk_4_0_9\packages\ti\csl\src\ip\serdes_sb\V0" this path we don't have required file (We have only configuration files for 5, 6.25, 10 and 12.

5).

Regards,

Nithin

0 Pavel Botev over 7 years ago in reply to Nithin kumar24

TI__Guru**** 170625 points

Nithin kumar24 said:

When we set "hyplnk_EXAMPLE_SERRATE_03p125" in code "hyplnkLLDConfig.h" file, link rate and lane rate are set as below

#elif defined hyplnk_EXAMPLE_SERRATE_03p125

linkRate = CSL_SERDES_LINK_RATE_6p25G;

lane_rate = CSL_SERDES_LANE_HALF_RATE;

Nithin kumar24 said:

Hyperlink Serdes Common Init Complete

Hyperlink Serdes Lane 0 Init Complete

Hyperlink Serdes Lane 1 Init Complete

Hyperlink Serdes Lane 2 Init Complete

Hyperlink Serdes Lane 3 Init Complete

Waiting for other side to come up ( 0)

Other side device is not connected properly. This is a expected log for this case. Make sure you are running the Hyperlink example project on both K2H devices. The basic configuration is required for other side device, such as enabling the power domain and performing the SerDes configuration of the HyperLink.

Regards,
Pavel

0 Nithin kumar24 over 7 years ago in reply to Pavel Botev

Intellectual 905 points

Hi Pavel,

We are running same binary in both the processors.

In both processor logs we are getting same prints as above.

Regards,

Nithin

0 Pavel Botev over 7 years ago in reply to Nithin kumar24

TI__Guru**** 170625 points

Nithin,

From what I understand, when you run the example between K2H device 1 Hyperlink0 and K2H device 2 Hyperlink0, the example runs successful. But when you run the example between K2H device 1 Hyperlink1 and K2H device 2 Hyperlink1, the example fail. And you have tested Hyperlink1 with SERRATE_03p125 and SERRATE_06p250. I can suggest you the below debug hints:

- try with SERRATE_01p250
- check Debug FAQ of the hyplnk wiki
- check Hyperlink1 pins (transmit/receive data pins, sideband signal pins) and compare with Hyperlink0
- check Hyperlink1 registers (local/remote config, SerDes config) and compare with Hyperlink0

Regards,
Pavel

0 Nithin kumar24 over 7 years ago in reply to Pavel Botev

Intellectual 905 points

Hi Pavel,

I used "SERRATE_01p250"

we are getting log as below

Version #: 0x02010007; string HYPLNK LLD Revision: 02.01.00.07:May 25 2018:11:00:09

About to do system setup (PLL, PSC, and DDR)

Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95

system setup worked

About to set up HyperLink Peripheral

============================Hyperlink Testing Port 1

========================================== begin registers before initialization ===========

Revision register contents:

Raw = 0x4e902101

Status register contents:

Raw = 0x00003004

Link status register contents:

Raw = 0x00000000

Control register contents:

Raw = 0x00000000

Control register contents:

Raw = 0x00000000

============== end registers before initialization ===========

Invalid Serdes Init Params : 2

This is because, in "C:\ti\pdk_k2hk_4_0_9\packages\ti\csl\src\ip\serdes_sb\V0" this path we don't have required file (We have only configuration files for 5, 6.25, 10 and 12.

5).

Meanwhile I'm checking those links which you mentioned in above reply.

Regards,

Nithin

0 Nithin kumar24 over 7 years ago in reply to Nithin kumar24

Intellectual 905 points

Hi Pavel,

Hyperlink1 is also working with 6.25 FULL Rate.

Now I need to test both Hyperlink1 and 0 simultaneously.

Do we have any application which I can reuse for my purpose ??!

Regards,

Nithin

0 Pavel Botev over 7 years ago in reply to Nithin kumar24

TI__Guru**** 170625 points

Nithin,

I am not able to find sample application that use both Hyperlink ports at the same time. Actually we have only one hyperlink sample application, the one described in the below wiki:

processors.wiki.ti.com/.../Processor_SDK_RTOS_HYPLNK

You have to re-work that application to enable both Hyperlink ports at the same time.

Regards,
Pavel

0 Nithin kumar24 over 7 years ago in reply to Pavel Botev

Intellectual 905 points

Hi Pavel,

I will reuse this application to test both Hyperlink1 and Hyperlink0 simultaneously.

For now I will close this query. Will be back if I face any problem during simultaneous testing.

Regards,

Nithin

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RTOS/66AK2H14: 66AK2H14 Hyperlink issue with TMS320C6678